Browsing by Author "Chen, Shi-Hao"

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An Efficient Hamiltonian-Cycle Power-Switch Routing for MTCMOS Designs
(2012)
Wang, Yi-Ming
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Chen, Shi-Hao
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Chao, Mango C. -T.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Multi-threshold CMOS (MTCMOS) is currently the most popular methodology in industry for implementing a power gating design, which can effectively reduce the leakage power by turning off inactive circuit domains. However, large peak current may be consumed in a power-gated domain during its sleep-to-active mode transition. As a result, major IC foundries recommend turning on power switches one by one to reduce the peak current during the mode transition, which requires a Hamiltonian-cycle routing to serially connect all the power switches. In this paper, we propose an efficient power-switch routing framework, which can effectively and efficiently find a feasible Hamiltonian-cycle routing among power switches without violating the Manhattan distance constraint between any two power switches while handling the irregular placement of the power switches resulting from the hard macros. The proposed framework is compliant to commercial APR tools and has been used in a major design-service company for taping out complex MTCMOS designs.
Cost-Effective Decap Selection for Beyond Die Power Integrity
(2014-01-01)
Chen, Yi-En
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Tsai, Tu-Hsiung
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Chen, Shi-Hao
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Chen, Hung-Ming
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電子工程學系及電子研究所
In designing reliable power distribution networks (PDN) for power integrity (PI), it is essential to stabilize voltage supply to devices on chip. We usually employ decoupling capacitor (decap) to suppress the noise generated by the switching of devices. There have been numerous prior works on how to select/insert decaps in chip, package, or board to maintain PI, however optimal decap selection is usually not applicable due to design budget and manufacturability. Moreover, design cost is seldom touched or mentioned. In this research, we propose an efficient methodology "PDC-PSO" to automatically optimizing the selection of available decaps. This algorithm not only takes advantage of particle swarm optimization (PSO) to stochastically search the design space, but takes the most effective range of decaps into consideration to outperform the basic PSO. We apply this to three real package designs and the results show that, compared to the original decap selection by rules of thumb, our approach could shorten the design period and we have better combination of decaps at the same or lower cost. In addition, our methodology can also consider package-board co-design in optimizing different operation frequencies.
Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs
(2019-01-01)
Wang, Yu-Zhe
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Wu, Jingjie
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Chen, Shi-Hao
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Chao, Mango Chia-Tso
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Yang, Chia-Hsiang
Cryptocurrencies have recently gained a lot of attention because their high security and easy transaction. Among the current cryptocurrencies, Bitcoin is the most well-known one. Application-specific ICs (ASICs) have been developed in order to deliver high throughput for Bitcoin mining. However, power dissipation is an important issue considering it causes increased mining cost and creates excessive heat. This paper presents three optimization techniques in the micro-architecture level for Bitcoin mining: deep pipelining, speculative computation, and approximate addition. The computations for Bitcoin milling are dominated by SHA-256, which can be realized by two-way 32-stage pipelines. Deep pipelining reduces the critical-path delay, resulting in less power due to architecture transformation and transistor sizing. The iterations of SHA-256 can be early terminated by leveraging speculative computation to prevent unnecessary switches. Approximate addition is adopted to reduce the critical-path delay of the compressor and expander at the cost of negligible precision loss. From the synthesis estimates at a 40-nm technology node, an overall 59.3% power reduction is achieved by applying these three techniques.
On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer
(2012-01-01)
Hsu, Hsin-Wu
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Chen, Meng-Ling
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Chen, Hung-Ming
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Li, Hung-Chun
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Chen, Shi-Hao
Due to the advantage of flip-chip design in power distribution but controversial peripheral 10 placement in lower design cost, redistribution layer (RDL) is usually used for such interconnection. Sometimes RDL is so congested that the capacity for routing is insufficient. Routing therefore cannot be completed within a single layer even for manual routing. Although [2] proposed a routing algorithm that uses two layers of RDLs, but in practice the required routing area is a little more than one layer. We overcome this problem by adopting the concept of pseudo single-layer. With the heuristics for routing on mapped channels and observations on staggered pins to relieve vertical constraints, the area of 2-layer routing can be minimized and the routability is 100%. Comparisons of routing results between manual design, the commercial tool, and the proposed method are presented. We have shown the effectiveness on a real industrial case: it originally required fully manual design, the proposed method can finish RDL routing automatically and effectively.
Power-Switch Routing for Reducing Dynamic IR Drop in Multi-Domain MTCMOS Designs
(2014-01-01)
Wang, Yi-Ming
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Chao, Mango C. -T.
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Chen, Shi-Hao
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Li, Hung-Chun
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電子工程學系及電子研究所
This paper presents a switch-routing framework which can generate a feasible Hamiltonian-path switch routing while minimizing the dynamic IR drop of a targeted fragile active domain with an analytical model. The accuracy of the analytical model and the effectiveness of the proposed framework are validated through an advanced multi-domain mobile-phone MTCMOS design.
Power-Up Sequence Control for MTCMOS Designs
(2013-03-01)
Chen, Shi-Hao
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Lin, Youn-Long
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Chao, Mango C. -T.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Power gating is effective for reducing standby leakage power asmulti-thresholdCMOS(MTCMOS) designs have become popular in the industry. However, a large inrush current and dynamic IR drop may occur when a circuit domain is powered up with MTCMOS switches. This could in turn lead to improper circuit operation. We propose a novel framework for generating a proper power-up sequence of the switches to control the inrush current of a power-gated domain while minimizing the power-up time and reducing the dynamic IR drop of the active domains. We also propose a configurable domino-delay circuit for implementing the sequence. Experimental results based on state-of-the-art industrial designs demonstrate the effectiveness of the proposed framework in limiting the inrush current, minimizing the power-up time, and reducing the dynamic IR drop. Results further confirm the efficiency of the framework in handling large-scale designs with more than 80 K power switches and 100 M transistors.
Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer
(2014-05-01)
Chang, Wen-Hsiang
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Chao, Mango C. -T.
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Chen, Shi-Hao
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a novel framework to efficiently and effectively build a robust but routing-friendly multilayer power network under the IR-drop and electro-migration (EM) constraints. The proposed framework first considers the impact of the aluminum-pad layer and provides a conservative analytical model to determine the total metal width for each power layer that can meet the IR-drop and EM constraints. Then the proposed framework can identify an optimal irredundant stripe width by considering the number of occupied routing tracks and the potential routing detour caused by the power stripes without the information of cell placement. Next, after the cell placement is done, the proposed framework applies a dynamic-programming approach to further reduce the potential routing detour by relocating the power stripes. A series of experiments are conducted based on a 40 nm, 1.1 V, and 900-MHz microprocessor to validate the effectiveness and efficiency of the proposed framework.
Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer
(2014-05-01)
Chang, Wen-Hsiang
;
Chao, Mango C. -T.
;
Chen, Shi-Hao
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a novel framework to efficiently and effectively build a robust but routing-friendly multilayer power network under the IR-drop and electro-migration (EM) constraints. The proposed framework first considers the impact of the aluminum-pad layer and provides a conservative analytical model to determine the total metal width for each power layer that can meet the IR-drop and EM constraints. Then the proposed framework can identify an optimal irredundant stripe width by considering the number of occupied routing tracks and the potential routing detour caused by the power stripes without the information of cell placement. Next, after the cell placement is done, the proposed framework applies a dynamic-programming approach to further reduce the potential routing detour by relocating the power stripes. A series of experiments are conducted based on a 40 nm, 1.1 V, and 900-MHz microprocessor to validate the effectiveness and efficiency of the proposed framework.
Routability-Driven Bump Assignment for Chip-Package Co-Design
(2014-01-01)
Chen, Meng-Ling
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Tsai, Tu-Hsiung
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Chen, Hung-Ming
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Chen, Shi-Hao
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電子工程學系及電子研究所
In current chip and package designs, it is a bottleneck to simultaneously optimize both pin assignment and pin routing for different design domains (chip, package, and board). Usually the whole process costs a huge manual effort and multiple iterations thus reducing profit margin. Therefore, we propose a fast heuristic chip-package co-design algorithm in order to automatically obtain a bump assignment which introduces high routability both in RDL routing and substrate routing (100% in our real case). Experimental results show that the proposed method (inspired by board escape routing algorithms) automatically finishes bump assignment, RDL routing and substrate routing in a short time, while the traditional co-design flow requires weeks even months.
Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators
(2016-05)
Mu, Szu-Pang
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Chao, Mango C. -T.
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Chen, Shi-Hao
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Wang, Yi-Ming
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電子工程學系及電子研究所
This paper presents a model-fitting framework to correlate the on-chip measured ring-oscillator counts to the chip\'s maximum operating speed. This learned model can be included in an auto test equipment (ATE) software to predict the chip speed for speed binning. Such a speed-binning method can avoid the use of applying any functional test and, hence, result in a third-order test time reduction with a limited portion of chips placed into a slower bin compared with the conventional functional-test binning. This paper further presents a novel builtin self-speed-binning system, which embeds the learned chip-speed model with a built-in circuit such that the chip speed can be directly calculated on-chip without going through any offline ATE software, achieving a fourth-order test-time reduction compared with the conventional speed binning. The experiments were conducted based on 360 test chips of a 28-nm, 0.9 V, 1.6-GHz mobile-application system-on-chip.
Testing Methods for Detecting Stuck-open Power Switches in Coarse-Grain MTCMOS Designs
(2010)
Mu, Szu-Pang
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Wang, Yi-Ming
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Yang, Hao-Yu
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Chao, Mango C. -T.
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Chen, Shi-Hao
Coarse-grain multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS power switches. In this paper, we study the usage of coarse-grain MTCMOS power switches for both logic circuits and SRAMs, and then propose corresponding methods of testing stuck-open power switches for each of them. For logic circuits, a specialized ATPG framework is proposed to generate a longest possible robust test while creating as many effective transitions in the switch-centered region as possible. For SRAMs, a novel test algorithm is proposed to exercise the worst-case power consumption and performance when stuck-open power switches exist. The experimental results based on an industrial MTCMOS technology demonstrate the advantage of our proposed testing methods on detecting stuck-open power switches for both logic circuits and SRAMs, when compared to conventional testing methods.
Testing Retention Flip-flops in Power-gated Designs
(2013)
Hsu, Hao-Wen
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Kuo, Shih-Hua
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Chang, Wen-Hsiang
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Chen, Shi-Hao
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Chang, Ming-Tung
This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-V-DD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention flip-flop during the restore function. To solve the first problem, we propose a novel ATPG framework to generate repeatedly toggling pattern pairs that can create maximal virtual-V-DD drop for a cycle. To solve the second problem, we propose a new test procedure to avoid the unintended initial value of the retention flip-flop after restoring. The effectiveness of the proposed ATPG framework and the new test procedure will be validated through SPICE simulation based on an industrial MTCMOS cell library.