Browsing by Author "Chen, Shih-Chang"

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Impact of Charge Trapping Effect on Negative Bias Temperature Instability in P-MOSFETs with HfO(2)/SiON Gate Stack
(2008)
Chen, Shih-Chang
;
Chien, Chao-Hsin
;
Lou, Jen-Chung
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In our study, we systematically investigated the behavior of charge trapping in P-MOSFETs with HfO(2)/SiON gate stack. We found that typical linear extrapolation does not work well for the lifetime extraction at normal operation condition since the polarity of dominant trapped charge in high-kappa dielectric is not the same at lower and higher stress voltage regimes. This phenomenon is considered the competition of hole trapping and electron trapping with respect to applied gate voltages. Besides, the results of AC stress reveal the distinct responses to electrons and holes. It indicates that electrons can easily follow the AC signal while holes seem to need more time for the response at AC stress.
Improvements of ozone surface treatment on the electrical characteristics and reliability in HfO2 gate stacks
(2007-09-01)
Chen, Shih-Chang
;
Chen, Yung-Yu
;
Chang, Yu-Tzu
;
Lou, Jen-Chung
;
Kin, Kon-Tsu
In this study, we improved the interfacial properties of high-kappa gate stacks with the surface treatment of ozonated water prior to deposition of hafnium oxide (HfO2). We demonstrated that the Ozone-oxide improved the electrical properties of the HfO2 gate stack interface in terms of its smoother interface, lower leakage current density, narrower hysteresis width, superior charge trapping effect, and reliability. From these experimental results, we believe that treatment with ozone is an efficient method for the preparation of high-quality interfaces between HfO2 and silicon surfaces.
Spatial and energetic distribution of border traps in the dual-layer HfO2/SiO2 high-k gate stack by low-frequency capacitance-voltage measurement
(2006-10-16)
Wu, Wei-Hao
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Tsui, Bing-Yue
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Chen, Mao-Chieh
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Hou, Yong-Tian
;
Jin, Yin
Threshold voltage instability measured by the pulse current-voltage technique has been recognized as the transient charging and discharging of the preexisting bulk traps in Hf-based high-k gate dielectrics, and these high-k traps or called border traps can instantly exchange charge carriers with the underlying Si substrate by tunneling through the thin interfacial oxide. Based on an elastic tunneling model through trapezoidal potential barriers, the spatial and energetic distribution of border traps in the HfO2/SiO2 high-k gate stack can be profiled as a smoothed, three-dimensional mesh by measuring the low-frequency capacitance-voltage characteristics of high-k metal-oxide-semiconductor capacitors with n-type Si substrate.
Transient charging and discharging behaviors of border traps in the dual-layer HfO2/SiO2 high-k gate stack observed by using low-frequency charge pumping method
(2007-06-01)
Wu, Wei-Hao
;
Tsui, Bing-Yue
;
Chen, Mao-Chieh
;
Hou, Yong-Tian
;
Jin, Yin
Transient charging and discharging of border traps in the dual-layer HfO2/SiO2 high-kappa. gate stack have been extensively studied by the low-frequency charge pumping method with various input pulse waveforms. It has been demonstrated that the exchange of charge carriers mainly occurs through the direct tunneling between the Si conduction band states and border traps in the HfO2 high-kappa. dielectric within the transient charging and discharging stages in one pulse cycle. Moreover, the transient charging and discharging behaviors could be observed in the time scale of 10(-8)-10(-4) s and well described by the charge trapping/detrapping model with dispersive capture/emission time constants used in static positive bias stress. Finally, the frequency and voltage dependencies of the border trap area density could also be transformed into the spatial and energetic distribution of border traps as a smoothed 3-D mesh profiling.