Browsing by Author "Chen, Shih-Hung"

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Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits
(2007-09-01)
Chen, Shih-Hung
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-mu m CMOS technology to achieve 1-kV CDM ESD robustness. (C) 2007 Elsevier Ltd. All rights reserved.
Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD Stresses
(2008-09-01)
Chen, Shih-Hung
;
Ker, Ming-Dou
;
Hung, Hsiang-Pin
;
電機學院
;
College of Electrical and Computer Engineering
Several complex electrostatic discharge (ESD) failure mechanisms have been found in the interface circuits of an IC product with multiple separated power domains. In this case, the machine-model (MM) ESD robustness cannot achieve 150 V in this IC product with separated power domains, although it can pass the 2-kV human-body-model (HBM) ESD test. The negative-to-VDD (ND) mode MM ESD currents were discharged by circuitous current paths through interface circuits to cause the gate oxide damage, the junction filament, and the contact destruction of the internal transistors. The detailed discharging paths of ND-mode ESD failures were analyzed in this paper. In addition, some ESD protection designs have been illustrated and reviewed to further comprehend the protection strategies for cross-power-domain ESD events. Moreover, one new active ESD protection design for the interface circuits between separated power domains has been proposed and successfully verified in a 0.13-mu m CMOS technology. The HBM and MM ESD robustness of the separated-power-domain interface circuits with the proposed active ESD protection design can achieve over 4 kV and 400 V, respectively.
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs
(2009-05-01)
Chen, Shih-Hung
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
The RC-based power-rail electrostatic-discharge (ESD) clamp circuit with big field-effect transistor (BigFET) layout style in the main ESD clamp n-channel metal-oxide-semiconductor (NMOS) transistor was widely used to enhance the ESD robustness of a CMOS IC fabricated in advanced CMOS processes. To further reduce the occupied layout area of the RC in the power-rail ESD clamp circuit, a new ESD-transient detection-circuit realized with smaller capacitance has been proposed and verified in a 0.13-mu m CMOS process. From the experimental results, the power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit can achieve a long-enough turn-on duration and higher ESD robustness under ESD stress condition, as well as better immunity against mistrigger and latch-on event under the fast-power-on condition.
DESIGN OF ON-CHIP POWER-RAIL ESD CLAMP CIRCUIT WITH ULTR-SMALL CAPACITANCE TO DETECT ESD TRANSITION
(2009)
Chen, Shih-Hung
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
A power-rail ESD clamp circuit with a new proposed ESD-transient detection circuit which adopts a ultra small capacitor to achieve the required functions has been presented and substantiated to own a long turn-on duration and high turn-on efficiency. In addition, the power-rail ESD clamp circuits with the new proposed ESD-transient detection circuit also presented an excellent immunity against the mis-trigger and the latch-on event under the fast power-on condition.
High-Performance Recessed-Channel Germanium Thin-Film Transistors via Excimer Laser Crystallization
(2018-03-01)
Liao, Chan-Yu
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Chen, Shih-Hung
;
Huang, Wen-Hsien
;
Shen, Chang-Hong
;
Shieh, Jia-Min
This letter demonstrates the excimer laser crystallization (ELC) of germanium (Ge) thin films with the recessed-channel (RC) structure for high-performance p-channel Ge thin-film transistors (TFTs). Using ELC, large longitudinal grainswith a single perpendicular grain boundary (GB) in the center of the recessed region were formed. This can be attributed to the lateral grain growth from unmelted Ge solid seeds in the thick region toward the complete melting recessed region during ELC. Consequently, the proposed p-channel RC-ELC Ge TFTs possessing large longitudinal grains without the perpendicular GB in the channel region exhibited a superior field-effect holemobility of 447 cm(2)V(-1)s(-1) with minor performance deviation.
Implementation of initial-on ESD protection concept with PMOS-triggered SCR devices in deep-submicron CMOS technology
(2007-05-01)
Ker, Ming-Dou
;
Chen, Shih-Hung
;
電機學院
;
College of Electrical and Computer Engineering
In order to enhance the applications of SCR devices for deep-submicron CMOS technology, a novel SCR design with "initial-on" function is proposed to achieve the lowest trigger voltage and the highest turn-on efficiency of SCR device for effective on-chip ESD protection. Without using the special native device (NMOS with almost zero or even negative threshold voltage) or any process modification, this initial-on SCR design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes. This initial-on SCR design has a high enough holding voltage to avoid latchup issues in a VDD operation voltage of 2.5 V. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a fully-silicided 0.25-mu m CMOS process.
Influence of InGaP and AlGaAs Schottky Layers on ESD Robustness in GaAs pHEMTs
(2012-09-01)
Chen, Shih-Hung
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Lin, Yueh-Chin
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Linten, Dimitri
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Scholz, Mirko
;
Hellings, Geert
GaAs high-electron-mobility transistors (HEMTs) have been widely used for radio-frequency (RF) applications due to the excellent material properties. One of the essential elements of the HEMTs is the gate Schottky barrier layer. InGaP has been proposed and proven as a better Schottky barrier material for the RF performance of the GaAs HEMTs. This letter investigates the influence of the GaAs HEMTs with two different Schottky layers, which are InGaP and AlGaAs on device transient characteristics under electrostatic discharge (ESD) stress. Although InGaP presents significant advantages on improving RF performance of GaAs HEMTs, it shows inferiority in ESD robustness.
Initial-on ESD protection design with PMOS-triggered SCR device
(2005)
Ker, Ming-Dou
;
Chen, Shih-Hung
;
電機學院
;
College of Electrical and Computer Engineering
A novel SCR design with "initial-on" function is proposed to achieve the lowest trigger voltage and the fastest turn-on speed of SCR device for effective on-chip ESD protection. Without using the special native device or any process modification, this initial-on design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes. This initial-on SCR design also presents a high enough holding voltage to avoid latchup issue. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a 0.25-mu m CMOS process.
Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-mu m CMOS technology
(2010-06-01)
Chen, Shih-Hung
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection capability. All of them are usually based on a similar circuit scheme with multiple-stage inverters to drive the main ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage inverter and 1-stage inverter controlling circuits have been studied to verify the optimal circuit schemes in the NMOS-based power-rail ESD clamp circuits Besides, the circuit performances among the main ESD clamp NMOS transistors drawn in different layout styles cooperated with the controlling circuit of 3-stage inverters or 1-stage inverter are compared. Among the NMOS-based power-rail ESD clamp circuits, an abnormal latch-on event has been observed under the EFT test and fast power-on condition. The root cause of this latch-on failure mechanism has been clearly explained by the emission microscope with InGaAs FPA detector. (C) 2010 Elsevier Ltd All rights reserved.
Local CDM ESD Protection Circuits for Cross-Power Domains in 3D IC Applications
(2014-06-01)
Chen, Shih-Hung
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Linten, Dimitri
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Scholz, Mirko
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Huang, Yu-Ching
;
Hellings, Geert
CDM ESD events can be a potential threat to SoC designs or heterogeneous 3D ICs with multiple power domains. Inter-layer ( or interface) circuits may need a local CDM ESD clamp that can prevent the unexpected failure under CDM ESD stress. In this letter, two local CDM ESD clamp circuits are proposed. They show better clamping efficiency under 2-ns vfTLP stress.
Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-mu m CMOS technology
(2007)
Chen, Shih-Hung
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
PMOS-triggered SCR devices with initial-on function have been proposed to achieve an efficient ESD protection in deep-submicron CMOS technology. The channel length of the embedded PMOS transistor in the PMOS-triggered SCR device dominates the trigger mechanism to govern the trigger voltage, holding voltage, turned-on resistance, second breakdown current, turn-on efficiency, and ESD robustness of the PMOS-triggered SCR device. The channel lengths of the embedded PMOS transistors in the PMOS-triggered SCR devices should be optimized to achieve the most efficient ESD protection design in deep-submicron or nanoscale CMOS technology.
Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection
(2009-07-01)
Chen, Shih-Hung
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.
RF/High-Speed I/O ESD Protection: Co-optimizing Strategy Between BEOL Capacitance and HBM Immunity in Advanced CMOS Process
(2020-07-01)
Wu, Wei-Min
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Ker, Ming-Dou
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Chen, Shih-Hung
;
Chen, Jie-Ting
;
Linten, Dimitri
In order to meet the requirement of ultrahigh-speed, low latency, and wide bandwidth (BW) in the next 5G mobile network and internet of things (IoT) applications, the parasitic capacitance specification of electrostatic discharge (ESD) protection devices should become much stricter. Reducing the capacitance always degrades the ESD performance in terms of shrinking the size of the ESD protection device. The distributed ESD protection network is one of the solutions which mitigates the capacitance issue and provides a broadband design. However, while the ESD devices are put under the I/O pad in the distributed ESD protection network, back-end-of-line (BEOL) capacitance starts to play an important role in the advanced 28-nm CMOS process. Therefore, a tapered metal structure is proposed to significantly reduce 30% BEOL capacitance of the ESD device, which can gain a 2.8-GHz increase in the operational BW in the distributed network. Meanwhile, it can enhance the human-body-model (HBM) level up to 16% higher than the original layout style under the same front-end-of-line (FEOL) layout size.