Browsing by Author "Chen, Shih-Lun"

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A Convolutional Neural Network Approach for Dental Panoramic Radiographs Classification
(2017-12-01)
Kuo, Yu-Fang
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Lin, Szu-Yin
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Wu, Calvin H.
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Chen, Shih-Lun
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Lin, Ting-Lan
Dental Panoramic Radiograph (DPR) has been widely accepted in the dental industry in recent years for providing valuable information to dental practitioners. Conventional fashion of analyzing this information has always been relying on the professional individuals. Nonetheless, the recent technology breakthrough with computer vision is promising in reducing effort and labor costs. The purpose of this study is to propose an automated DPR classification method that could be used to identify condition such as having undergone endodontic therapy. This new method used a combination of unique preprocessing procedure with highly developed image recognition algorithm known as Convolutional Neural Network (CNN). The new method firstly preprocesses and normalizes the DPR images as the training dataset, then trains the network model using the training data. Finally, testing datasets will then be used for generating evaluation results. Based from the experimental results, the trained network with preprocessed training datasets performed an accuracy rate of 85.3%. In addition, the performance of the network could still be improved by increasing the number of training datasets and using more preprocessing methods. In conclusion, computer visions can provide confident better performance in DPR classification in practices such as DPR classification.
An output buffer for 3.3-V applications in a 0.13-mu m 1/2.5-V CMOS process
(2007-01-01)
Chen, Shih-Lun
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Ker, Ming-Dou
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電機學院
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College of Electrical and Computer Engineering
With a 3.3-V interface, such as PCI-X application, high-voltage overstress on the gate oxide is a serious reliability problem in designing I/O circuits by using only 1/2.5-V low-voltage devices in a 0.13-mu m CMOS process. Thus, a new output buffer realized with low-voltage (1- and 2.5-V) devices to drive high-voltage signals for 3.3-V applications is proposed in this paper. The proposed output buffer has been fabricated in a 0.13-mu m 1/2.5-V 1P8M CMOS process with Cu interconnects. The experimental results have confirmed that the proposed output buffer can be successfully operated at 133 MHz without suffering high-voltage gate-oxide overstress in the 3.3-V interface. In addition, a new level converter that is realized with only 1- and 2.5-V devices that can convert 0/1-V voltage swing to 1/3.3-V voltage swing is also presented in this paper. The experimental results have also confirmed that the proposed level converter can be operated correctly.
Automated knowledge discovery and semantic annotation for network and web services
(2016-07-01)
Lin, Szu-Yin
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Chung, Chia-Chen
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Hu, Wei-Che
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Hung, Chihli
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Chen, Shih-Lun
With the rise of the Internet of things, the smart environmental issue is becoming increasingly important. Sensor web is one of the best solutions to this issue and provides the advantages of sensor networks and web services. Ontology web language for services (OWL-S) is an OWL-based web services ontology, which provides the ability to describe the semantics of web services and their capabilities in a formal and machine-processable manner. Moreover, it aids semantic service matching, selection and composition. However, automatically annotating semantic web services is a highly complicated and tedious task. In this study, we propose a methodology to uncover information in the history data and profiles of web services and then semantically annotate them. With the proposed approach, semantic relationships between web services could be extracted via a combination of association rules and input/ output matching. Our results show that this hybrid automated knowledge-discovery approach works better than traditional approaches do. We also provide a scenario to explain how the proposed methodology works.
Design of mixed-voltage I/O buffer by using NMOS-blocking technique
(2006-10-01)
Ker, Ming-Dou
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Chen, Shih-Lun
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電機學院
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College of Electrical and Computer Engineering
An nMOS-blocking technique for mixed-voltage I/O buffer realized with only 1 x V-DD devices can receive 2 x V-DD, 3 x V-DD, and even 4 x V-DD input signal without the gate-oxide reliability issue is proposed. In this paper, the 2 x V-DD input tolerant mixed-voltage I/O buffer by using the nMOS-blocking technique has been verified in a 0.25-mu m 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface. The 3 x V-DD input tolerant mixed-voltage I/O buffer by using the nMOS-blocking technique has been verified in a 0.13-mu m 1-V CMOS process to serve 1/3-V mixed-voltage interface. The proposed nMOS-blocking technique can be extended to design the 4 x V-DD, 5 x V-DD, and even 6 x V-DD input tolerant mixed-voltage I/O buffers. The limitation of the nMOS-blocking technique is the breakdown voltage of the pn-junction in the given CMOS process.
Mixed voltage input/output buffer having low-voltage design
(2007-11-29)
Ker, Ming-Dou
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Chen, Shih-Lun
A mixed-voltage input/output buffer having low-voltage design comprises a pre-driver, a tracking unit, a driving unit, and input/output pad, a floating-well unit and a transporting unit. The pre-driver receives first data signal and enable signal and outputs first and second data voltages. The tracking unit provides Gate-Tracking function. The driving unit couples the pre-driver and the tracking unit for production of a first buffer voltage corresponding to the first data voltage. The input/output pad couples the driving unit to output a first buffer voltage and to receive a second data signal. The output unit is used for outputting a second buffer voltage corresponding to the second data signal. The floating-well unit couples to the driving unit and the input/output pad in order to output first buffer voltage and receive second data signal. The floating-well unit is used for preventing leakage current.
On-chip high-voltage charge pump circuit in standard CMOS processes with polysilicon diodes
(2005)
Ker, Ming-Dou
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Chen, Shih-Lun
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電機學院
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College of Electrical and Computer Engineering
An on-chip high-voltage charge pump circuit realized with the polysilicon diodes in standard (bulk) CMOS process is presented in this paper. Because the polysilicon diodes are fully isolated from the substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS processes without extra process steps. The proposed charge pump circuit has been fabricated in a 0.25-mu m 2.5-V standard CMOS process. The output voltage of the 12-stage charge pump circuit can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (18.9 V) in a 0.25-mu m 2.5-V standard CMOS process.
Overview and design of mixed-voltage I/O buffers, with low-voltage thin-oxide CMOS transistors
(2006-09-01)
Ker, Ming-Dou
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Chen, Shih-Lun
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Tsai, Chia-Sheng
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電機學院
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College of Electrical and Computer Engineering
Overview on the prior designs of the mixed-voltage I/O buffers is provided in this work. A new 2.5/5-V mixed-voltage I/O buffer realized with only thin gate-oxide devices is proposed. The new proposed mixed-voltage I/O buffer with simpler dynamic n-well bias circuit and gate-tracking circuit can prevent the undesired leakage current paths and the gate-oxide -reliability problem, which occur in the conventional CMOS I/O buffer. The new mixed-voltage I/O buffer has been fabricated and verified in a 0.25-mu m CMOS process to serve 2.5/5-V I/O interface. Besides, another 2.5/5-V mixed-voltage I/O buffer without the subthreshold leakage problem for high-speed applications is also presented in this work. The speed, power consumption, area, and-noise among these mixed-voltage I/O buffers are also compared and discussed. The new proposed mixed-voltage I/O buffers can be easily scaled toward 0.18- mu m (or below) CMOS processes to serve other mixed-voltage I/O interfaces, such as 1.8/3.3-V interface.
Ultra-high-voltage charge pump circuit in low-voltage bulk CMOS processes with polysilicon diodes
(2007-01-01)
Ker, Ming-Dou
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Chen, Shih-Lun
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電機學院
;
College of Electrical and Computer Engineering
An on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes in the low-voltage bulk CMOS process is proposed in this work. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS processes without extra process steps. The proposed ultra-high-voltage charge pump circuit has been fabricated in a 0.25-mu m 2.5-V standard CMOS process. The output voltage of the four-stage charge pump circuit with 2.5-V power-supply voltage (VDD = 2.5 V) can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (similar to 18.9 V) in a 0.25-mu m 2.5-V bulk CMOS process.