Browsing by Author "Chen, Shin-Hao"

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11.25-ms-Group-Delay and Low-Complexity Algorithm Design of 18-Band Quasi-ANSI S1.11 1/3 Octave Digital Filterbank for Hearing Aids
(2015-06-01)
Lai, Shin-Chi
;
Liu, Chih-Hao
;
Wang, Ling-Yi
;
Chen, Shin-Hao
;
Chen, Ke-Horng
This paper presents a novel algorithm and architecture design for 18-band quasi-class-2 ANSI S1.11 1/3 octave filterbank. The proposed design has several advantages such as lower group delay, lower computational complexity, and lower matching error. The technique we developed in this paper can be summarized as follows: 1) a simple low-pass filter (LPF) and discrete cosine transform (DCT) modulation are utilized to generate a uniform 9-band filterbank first, and then all elements of are replaced by all-pass filters to obtain a non-uniform filterbank; 2) a fast recursive structure and variable-length algorithm is further developed to efficiently accomplish DCT modulation. Thus, the spectrum of LPF can be easily spanned and flexibly extended to the location of the desired central frequency; 3) after employing the multi-rate algorithm, an 18-band non-uniform filterbank is generated from two 9-band sub filterbanks by following the proposed design steps and parameter determinations. Compared with the latest Liu et al.\'s quasi-class-2 ANSI S1.11 design, the proposed method-I (Proposed-I) totally has 72.8% reduction for multiplications per sample, 11.25-ms group delay, and 59 additions decreased per sample. Moreover, the maximum matching error of the proposed method-II (Proposed-II) is averagely equal to 1.79 dB much smaller than that of the latest Wei et al.\'s design. For the proposed variable-length DCT modulation, only 2 adders, 2 multipliers, 2 multiplexers, and 5 registers are required for hardware implementation after applying VLSI retiming scheme. Overall, the proposed filterbank design would be a new solution for future applications in the area of hearing aids.
90% Peak Efficiency Single-Inductor-Multiple-Output DC-DC Buck Converter with Output Independent Gate Drive Control
(2015-01-01)
Su, Yi-Ping
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Lin, Chiun-He
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Peng, Shen-Yu
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Huang, Ru-Yu
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Yang, Te-Fu
99.4% Peak Audio Signal Recovery Rate and Ultra-Low 0.32dB Matching Error with 10Hz High Resolution Filter Fitting Wearable Aided Speech Compensation System
(2015)
Lin, Yen-Ting
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Lai, Shin-Chi
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Chen, Shin-Hao
;
Peng, Shen-Yu
;
Chen, Ke-Horng
to get high sound quality, the proposed adaptive speech compensation (ASC) system fits psychoacoustic curves for individual needs. Moreover, characteristics of the speakers are considered by real-time speaker impedance estimation (RT-SIE) technique. Hence, original signal can be restored for every user with any speakers. ASC system has 99.4% peak original signal recovery rate by predicting and controlling output signal precisely. And the built-in 10Hz high resolution acoustic filter fitting scheme (AFFS) has less than 0.32dB matching error with an over 80dB hearing loss.
A 2.5W Tablet Speaker Delivering 3.2W Pseudo High Power by Psychoacoustic Model Based Adaptive Power Management System
(2014)
Chen, Shin-Hao
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Peng, Shen-Yu
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Chen, Ke-Horng
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Lai, Shin-Chi
;
Kang, Sheng
for a 2.5W speaker in tablets, the proposed adaptive power management (APM) system can deliver a pseudo high power of 3.2W with a +/- 4V supply because it suppresses 0.7W power on tones that may damage a 2.5W speaker and escape the notice of human ears. With z-domain digital signal processing (z-DSP) and psychoacoustic model, high efficient power management and high sound quality can be achieved simultaneously. Conventional automatic gain control (AGC) only has the ability of 0.32W power suppression. Moreover, suppressing power by conventional clipping technique increases total-harmonic-distortion (THD). In contrast, the proposed real-time dynamic loading impedance (RT-DLI) monitoring brings forward a way to solve the problem on speaker damage while keeping low THD during high sound pressure level (SPL). THD in the APM system is slightly higher than that of original sound 1.1dB, comparing to the disadvantage of 8.6dB increasing caused by conventional clipping technique.
A Class-D Amplifier Powered by Embedded Single-Inductor Bipolar-Output Power Module with Low Common Noise and Dynamic Voltage Boosting Technique
(2014-01-01)
Chen, Shin-Hao
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Lin, Kuei-Liang
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Ng, Shao Siang
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Chen, Ke-Horng
;
Wey, Chin-Long
This paper proposes a high efficiency Class-D amplifier (CDA) with embedded single-inductor bipolar output (SIBO) power module. The characteristics of SIBO converter\'s bipolar outputs not only suppress equivalent common mode noise but also remove several large external bulky components in conventional boost supply CDA systems. Since bipolar outputs in the SIBO provide independent driving capability, CDA is capable of operating in both single-ended (SE) and bridge-tide load (BTL) configurations. Furthermore, the proposed dynamic voltage boosting (DVB) technique adjusts the SIBO output voltage level according to the CDA\'s output level with 5% power efficiency improvement. Peak total harmonic distortion plus noise (THD+N) performance is 0.012%. Peak power efficiency of SIBO and CDA are 89% and 93.2%, respectively.
A Direct AC-DC and DC-DC Cross-Source Energy Harvesting Circuit with Analog Iterating-Based MPPT Technique with 72.5% Conversion Efficiency and 94.6% Tracking Efficiency
(2016-08)
Chen, Shin-Hao
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Huang, Tzu-Chi
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Ng, Shao Siang
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Lin, Kuei-Liang
;
Du, Ming-Jhe
The proposed cross-source energy (CSE) harvesting system accepts universal energy sources, including the ac and dc sources. The buck-boost conversion of CSE automatically converts ac or dc input into dc output without being limited by the type of universal energy source. The CSE technique simultaneously supplies the regulated output for the system loading and the battery charging output. A test chip fabricated in the VIS Bipolar, CMOS, and DMOS (BCD) process can optimally derive harvest energy with 72.5% power efficiency when one solar input source is used. A backup converter is designed to complement the CSE technique to guarantee the regulation of output voltage. The proposed analog iterating-based (AIB) maximum power point tracking (MPPT) technique achieves 94.6% tracking efficiency without complex data calculation and storage, which are better results compared with those of previous research.
An Energy and Cost Efficient WDM/OFDMA PON System: Design and Demonstration
(2013-08-15)
Yuang, Maria C.
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Hsu, Dar-Zu
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Tien, Po-Lung
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Chen, Hsing-Yu
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Wei, Chia-Chien
In this paper, we propose an energy and cost efficient WDM/OFDMA PON system, referred to as NEWOPS. Based on a new two-tiered semi-tree architecture, NEWOPS allows a large number of ONUs to be connected to OLT using only a handful of colorless transceivers. Due to the architecture, NEWOPS not only facilitates high spectral efficiency and flexible sub-channel bandwidth allocation, but also reduces the Rayleigh backscattering (RB) problem and achieves high energy and cost efficiency. Experimental results demonstrate that, taking only 5-GHz bandwidth for each wavelength, NEWOPS successfully achieves 20-Gb/s downstream and 10-Gb/s upstream OFDM-xQAM transmissions via the same fiber trunk. We depict that, to support 40 ONUs for example, NEWOPS achieves energy efficiency that is three to six times higher than that of a typical 10-Gb/s WDM/OFDM PON.
Embedded Single-Inductor Bipolar-Output DC-DC Converter in Class-D Amplifier for Low Common Noise
(2016-04-01)
Chen, Shin-Hao
;
Lin, Kuei-Liang
;
Ng, Shao Siang
;
Huang, Tzu-Chi
;
Chen, Ke-Horng
This paper proposes a high efficiency class-D amplifier (CDA) with embedded single-inductor bipolar output (SIBO) power module. The characteristics of SIBO converter\'s bipolar outputs not only suppress equivalent common-mode noise but also remove several large external bulky components in conventional boost supply CDA systems. Since bipolar outputs in the SIBO provide independent driving capability, CDA is capable of operating in both single-ended and bridge-tide load configurations. Furthermore, the proposed dynamic voltage boosting technique adjusts the SIBO output voltage level according to the CDA\'s output level with 5% power efficiency improvement. Peak total harmonic distortion plus noise performance is 0.012%. Peak power efficiency of SIBO and CDA is 89% and 93.2%, respectively.
Hybrid Architecture Design for Calculating Variable-Length Fourier Transform
(2016-03)
Lai, Shin-Chi
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Juang, Wen-Ho
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Lee, Yueh-Shu
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Chen, Shin-Hao
;
Chen, Ke-Horng
This brief presents a hybrid structure to effectively compute the variable-length Fourier transform by employing the recursive and radix-2(2) fast algorithm. After applying a hardware-sharing scheme to both fast algorithms, the proposed method not only improves the drawback of higher hardware cost in implementation but also retains the regular and flexible nature of recursive discrete Fourier transform (RDFT). The proposed hardware accelerator only costs four real multipliers and ten real adders with a greater reduction (86.7% and 66.7%, respectively) than Kim et al.\'s design. In addition, the number of multiplications and additions for 256-point DFT computations can be reduced by 38.6% and 70%, respectively, compared to Lai et al.\'s recent approach. For accuracy analysis, the SNR value of the proposed design, at least, is 4 dB higher than the other RDFT designs. Considering a whole evaluation, a very-large-scale integration chip design was further fabricated using TSMC 0.18-mu m 1P6M CMOS process. The core size was only 660 x 660 mu m(2), and the measured power consumption was 8.8 mW @ 25 MHz. The result shows that the proposed chip included data memory is 1.38 times the computational efficiency per unit area of Lai et al.\'s work. Therefore, it will be the state-of-the-art RDFT processor in the application of various variable-transform-length digital signal processing issues.