Browsing by Author "Chen, Shin-Kai"

Now showing 1 - 9 of 9

A Low-Error and Rom-Free Logarithmic Arithmetic Unit for Embedded 3D Graphics Applications
(2013)
Lin, Tsung-Ching
;
Chen, Shin-Kai
;
Liu, Chih-Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
As the evolution of smart phone, 3D graphics become more and more important in mobile computing systems. Within 3D graphics, logarithmic arithmetic is usually utilized to simplify multiplication, division, and power operations. In this paper, we propose a low-error and Rom-free logarithmic arithmetic unit for 3D graphics applications. The logarithmic arithmetic unit applies non-uniform regional linear interpolation and compensation method for logarithmic converters. According to experiment results, proposed 2-region logarithmic converter reduces 48.0% error range and 42.1% percent error. 21.6% area and 13.8% power consumption are gained.
A Low-Error and Rom-Free Logarithmic Arithmetic Unit for Embedded 3D Graphics Applications
(2013-01-01)
Lin, Tsung-Ching
;
Chen, Shin-Kai
;
Liu, Chih-Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
As the evolution of smart phone, 3D graphics become more and more important in mobile computing systems. Within 3D graphics, logarithmic arithmetic is usually utilized to simplify multiplication, division, and power operations. In this paper, we propose a low-error and Rom-free logarithmic arithmetic unit for 3D graphics applications. The logarithmic arithmetic unit applies non-uniform regional linear interpolation and compensation method for logarithmic converters. According to experiment results, proposed 2-region logarithmic converter reduces 48.0% error range and 42.1% percent error. 21.6% area and 13.8% power consumption are gained.
A Low-Error, Cost-Efficient Design Procedure for Evaluating Logarithms to Be Used in a Logarithmic Arithmetic Processor
(2016-04)
Liu, Chih-Wei
;
Ou, Shih-Hao
;
Chang, Kuo-Chiang
;
Lin, Tzung-Ching
;
Chen, Shin-Kai
Based on an error-flattened, non-uniform-region linear-approximation algorithm, this brief proposes a low-error and a cost-efficient design procedure for realizing an optimized shift-and-add Logarithmic Unit (LU), which uses minimum hardware to meet the desired error constraint for embedded graphics systems. Mathematically, this brief first derives two solutions of the error-flattened algorithm. Subsequently, for an error constraint, the minimum number of approximation regions, n, the corresponding i th interpolation coefficients (a(i), b(i)), and the regional endpoints (x(i-1), x(i)), 1 <= i <= n, are obtained accordingly. Using the unique properties of the logarithmic function, spacing of x(i) is non-uniform to make errors in each region consistent. Carefully examining the cost of the applied add/sub network, a low-cost candidate for a shift-and-add LU is determined. Next, a cost exploration process, which gradually increases n, is performed. A large number of regions results in a more accurate conversion algorithm that might tolerate more implementation errors by using simple hardware whose cost is lower than that of the inferior candidate. After exploring the cost based on error tolerance, the proposed design procedure finally generates a hardware to meet the desired error constraint. Slightly modifying the regional endpoint x(i) increases hardware efficiency at the cost of increased error. Proposed circuits were synthesized in UMC 65RVT CMOS technology. Compared to state-of-the-art shift-and-add logarithmic converters, simulation results reveal that the proposed design saves approximately 12.7-51.1 percent area of polynomial approximation and improves approximately 1-14-dB SNR gain while achieving a tighter error constraint.
Design and implementation of a high-performance and complexity-effective VLIW DSP for multimedia applications
(2008-06-01)
Lin, Tay-Jyi
;
Chen, Shin-Kai
;
Kuo, Yu-Ting
;
Liu, Chih-Wei
;
Hsiao, Pi-Chen
This paper presents the design and implementation of a novel VLIW digital signal processor (DSP) for multimedia applications. The DSP core embodies a distributed & ping-pong register file, which saves 76.8% silicon area and improves 46.9% access time of centralized ones found in most VLIW processors by restricting its access patterns. However, it still has comparable performance (estimated in cycles) with state-of-the-art DSP for multimedia applications. A hierarchical instruction encoding scheme is also adopted to reduce the program sizes to 24.1 similar to 26.0%. The DSP has been fabricated in the UMC 0.13 mu m 1P8M Copper Logic Process, and it can operate at 333 MHz while consuming 189 mW power. The core size is 3.2 x 3.15 mm(2) including 160 KB on-chip SRAM.
Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM)
(2013-10-01)
Chen, Shin-Kai
;
Liu, Chih-Wei
;
Wu, Tsung-Yi
;
Tsai, An-Chi
;
電子工程學系及電子研究所
Data hazards cause severe pipeline performance degradation for data-intensive computing processes. To improve the performance under a pessimistic assumption on the pipeline efficiency, a high-speed and energy-efficient VLSBM is proposed that successively performs a speculating and correcting phase. To reduce the critical path, the VLSBM partial products are partitioned into the (n - z)-bit least significant part (LSP) and the self-reliant (n + z)-bit most significant part (MSP), and an estimation function stochastically predicts the carry to the MSP, thereby allowing independent calculation of the partial-product accumulation of parts. When a carry prediction is accurate, the data dependence is hidden and the correcting phase is bypassed, thereby ensuring the potential speed-up of the pipelined datapath. If a prediction is inaccurate, the speculation is flushed and the correcting phase is executed to obtain the exact multiplication. The simulation results verify the effectiveness of the proposed VLSBM. When applied to a DSP algorithm with a data hazard (or dependence) probability P-D, 0 <= P-D <= 1, the results show that the proposed VLSBM outperforms the original Booth multiplier and the fastest conventional well-pipelined modified Booth multiplier when P-D > 0.32. For the case of high P-D with P-D approximate to 1, the proposed VLSBM improves approximately 1.47 times speedup against the fastest conventional pipelined Booth multiplier (@ UMC 90 nm CMOS) and, furthermore, approximately 25.4% of energy per multiplication and 7% of area are saved. By examining multiplications during three multimedia application processes (i.e., JPEG compression, object detection, and H.264/AVC decoding), the proposed VLSBM improves the speed-up ratio by approximately 1.0 to 1.4 times, and reduces the cycle count ratio by approximately 1.3 to 1.8 times in comparison to the fastest conventional two-stage pipelined Booth multiplier.
MULTITASKING PROCESSOR AND TASK SWITCHING METHOD THEREOF
(2010-02-25)
Lin, Tay-Jyi
;
Huang, Pao-Jui
;
Liu, Chih-Wei
;
Chen, Shin-Kai
;
Wang, Bing-Shiun
A multitasking processor and a task switching method thereof are provided. The task switching method includes following steps. A first task is executed by the multitasking processor, wherein the first task contains a plurality of switching-point instructions. An interrupt event occurs. Accordingly, the multitasking processor temporarily stops executing the first task and starts to execute a second task. The multitasking processor executes a handling process of the interrupt event and sets a switching flag. After finishing the handling process of the interrupt event, the multitasking processor does not perform task switching but continues to execute the first task, and the multitasking processor only performs task switching to execute the second task when it reaches a switching-point instruction in the first task.
Parallel Object Detection on Multicore Platforms
(2009)
Chen, Shin-Kai
;
Lin, Tay-Jyi
;
Liu, Chih-Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Object detection is an important function for intelligent multimedia processing, but its computational complexity prevented its pervasive uses in consumer electronics. Cost-effective & energy-efficient computations are now available with various innovative multicore architectures proposed for embedded systems. However, extensive software optimizations are needed to unravel the inherent parallelisms in object detection for multicore processing. This paper presents interleaved reordering and splitting of parallel tasks in object detection. Overall performance improvements by 10% & 19% have been measured for the proposed methods respectively on a face detection prototype implemented on Sony PlayStation 3.
Parallelizing Complex Streaming Applications on Distributed Scratchpad Memory Multicore Architecture
(2014-12-01)
Chen, Shin-Kai
;
Hung, Cheng-Yu
;
Chen, Ching-Chih
;
Liu, Chih-Wei
;
交大名義發表
Multicore processors can provide sufficient computing power and flexibility for complex streaming applications, such as high-definition video processing. For less hardware complexity and power consumption, the distributed scratchpad memory architecture is considered, instead of the cache memory architecture. However, the distributed design poses new challenges to programming. It is difficult to exploit all available capabilities and achieve maximal throughput, due to the combined complexity of inter-processor communication, synchronization, and workload balancing. In this study, we developed an efficient design flow for parallelizing multimedia applications on a distributed scratchpad memory multicore architecture. An application is first partitioned into streaming components and then mapped onto multicore processors. Various hardware-dependent factors and application-specific characteristics are involved in generating efficient task partitions and allocating resources appropriately. To test and verify the proposed design flow, three popular multimedia applications were implemented: a full-HD motion JPEG decoder, an object detector, and a full-HD H.264/AVC decoder. For demonstration purposes, SONY PlayStation3 was selected as the target platform. Simulation results show that, on PS3, the full-HD motion JPEG decoder with the proposed design flow can decode about 108.9 frames per second (fps) in the 1080p format. The object detection application can perform real-time object detection at 2.84 fps at resolution, 11.75 fps at resolution, and 62.52 fps at resolution. The full-HD H.264/AVC decoder applications can achieve nearly 50 fps.
Rapid C to FPGA prototyping with multithreaded emulation engine
(2007)
Chen, Shin-Kai
;
Wang, Bing-Shiun
;
Lin, Tay-Jyi
;
Liu, Chih-Wei
;
電子工程學系及電子研究所
FPGA prototyping is preferred over software simulations for its more convincing & realistic behaviours and fast simulation time. However, it is usually possible after the RTL design is done, which prevents extensive design space exploration. This paper describes an early-stage FPGA prototyping flow, which starts from C sources, through hardware/software partitioning with transaction-level modelling (TLM), to the RTL design. We also propose a FPGA-customized multithreaded emulation engine for TLM prototyping. Compared with the OpenRISC core, the proposed engine saves 43.08% datapath complexity while improving the operating frequency by 60.67%. Moreover, our FPGA prototype for JPEG at TLM can compress 37.16 color QCIF frames per second, which is 4.5X faster than SystemC simulation on a 3GRz PentiumD PC.