Browsing by Author "Chen, Shing-Yu"

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A Configurable Bus-Tracer for Error Reproduction in Post-Silicon Validation
(2013)
Chen, Shing-Yu
;
Hsiao, Ming-Yi
;
Jone, Wen-Ben
;
Chen, Tien-Fu
;
交大名義發表
In today's modern system-on-chips (SoCs), there are several intellectual properties (IPs) on the system to provide different functionality. However, the more complex communications on SoCs are, the harder the programmer could discover all errors before first silicon during verification. Therefore, we provide a reconfigurable unit for recording the transactions between IPs and adopt logical vector clock [1] as timestamp of each trace. The programmable trigger unit (PTU) in debugging node (DN) could be configured by the validator to cache their interest sequences of transaction. Because the traces of transactions would have their own timestamp, during the post-silicon validation, we could reproduce the errors in faulty transactions between IPs and get more information for bypassing or fixing the problems. Furthermore, due to several entries of traces, which would shrink observation window very quickly, we also implement a compressor to compress traces before we store them into trace buffer. Finally, our experiments demonstrate that the proposed debugging architecture is capable of recording the critical transactions, and by the proposed reconfigurable debugging unit the debugging execution time can be reduced more than 80%.
A Configurable Bus-Tracer for Error Reproduction in Post-Silicon Validation
(2013-01-01)
Chen, Shing-Yu
;
Hsiao, Ming-Yi
;
Jone, Wen-Ben
;
Chen, Tien-Fu
;
交大名義發表
In today's modern system-on-chips (SoCs), there are several intellectual properties (IPs) on the system to provide different functionality. However, the more complex communications on SoCs are, the harder the programmer could discover all errors before first silicon during verification. Therefore, we provide a reconfigurable unit for recording the transactions between IPs and adopt logical vector clock [1] as timestamp of each trace. The programmable trigger unit (PTU) in debugging node (DN) could be configured by the validator to cache their interest sequences of transaction. Because the traces of transactions would have their own timestamp, during the post-silicon validation, we could reproduce the errors in faulty transactions between IPs and get more information for bypassing or fixing the problems. Furthermore, due to several entries of traces, which would shrink observation window very quickly, we also implement a compressor to compress traces before we store them into trace buffer. Finally, our experiments demonstrate that the proposed debugging architecture is capable of recording the critical transactions, and by the proposed reconfigurable debugging unit the debugging execution time can be reduced more than 80%.
A High-Performance OFDMA PON System Architecture and Medium Access Control
(2012-06-01)
Yuang, Maria C.
;
Tien, Po-Lung
;
Hsu, Dar-Zu
;
Chen, Shing-Yu
;
Wei, Chia-Chien
Orthogonal frequency-division multiplexing (OFDM) passive optical network (PON) has been considered to be a promising next-generation broadband wired access solution. However, based on the current tree-based architecture, existing OFDM PON systems face severe challenges when increasing the scalability and data-rate performance. In this paper, we propose a high-performance virtual-tree orthogonal frequency-division multiple access PON system (VTOPS). With the virtual-tree architecture and coupled with the use of inexpensive direct modulation, VTOPS features high reliability, scalability, spectrum efficiency, and cost effectiveness all at once. For governing the flexible/fair access and dynamic allocation of bandwidth, VTOPS incorporates a rate-based medium access control (MAC) scheme. The MAC scheme performs dynamic rate adjustment using a neural-fuzzy system. By adjusting the system parameters, the MAC scheme can achieve a wide range of delay and fairness performance under a variety of traffic patterns. Finally, we show both theoretical and experimental results to demonstrate that, by applying the power pre-emphasis algorithm and adaptive subchannel modulation, VTOPS achieves 40 Gb/s downlink and 40 Gb/s uplink transmissions, using low-cost 10 GHz directly modulated lasers.
A Novel Passive Optical Network Architecture Supporting Seamless Integration of RoF and OFDMA Signals
(2010-03-15)
Lin, Yu-Min
;
Tien, Po-Lung
;
Yuang, Maria C.
;
Lee, Steven S. W.
;
Chen, Jason (Jyehong)
In this letter, we propose a novel passive optical network (PON) architecture supporting radio-over-fiber signals and orthogonal frequency-division multiple access (OFDMA) PON signals. The architecture transports upstream multiple remote antenna's wireless signals using only one upstream wavelength. In addition, the windowed-orthogonal frequency-division-multiplexing technique is employed to mitigate interference during the integration process. Experimental results shows that 10-Gb/s OFDMA and three radio-frequency signals at 2.1 GHz are successfully transmitted over 20-km single-mode fiber in a 32-optical-network-unit PON.