Browsing by Author "Chen, Shuang-Yuan"

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Gate-to-drain capacitance verifying the continuous-wave green laser crystallization n-TFT trapped charges distribution under dc voltage stress
(2009-12-21)
Hsieh, Zhen-Ying
;
Wang, Mu-Chun
;
Chen, Shuang-Yuan
;
Chen, Chih
;
Huang, Heng-Sheng
In this work, a metrology was proposed to realize the distribution of fixed oxide trapped charges and grain boundary trapped states. The (continuous-wave green laser crystallization) n-channel thin-film transistors (TFTs) were forced by dc voltage stress, V(G)=V(D). The gate-to-drain capacitance, C(GD) -V(G), with varying frequency of applied small signal was developed. To probe the distribution of these defects, the difference (initial capacitance values minus stressed capacitance values) of C(GD) -V(G) with different frequencies was precisely studied. (C) 2009 American Institute of Physics. [doi:10.1063/1.3275728]
Trend transformation of drain-current degradation under drain-avalanche hot-carrier stress for CLC n-TFTs
(2009-08-01)
Hsieh, Zhen-Ying
;
Wang, Mu-Chun
;
Chen, Chih
;
Shieh, Jia-Min
;
Lin, Yu-Ting
Continuous-wave green laser-crystallized (CLC) single-grain-like polycrystalline silicon n-channel thin-film transistors (poly-Si n-TFTs) demonstrate the higher electron mobility and turn-on current than excimer laser annealing (ELA) poly-Si n-TFTs. Furthermore, high drain voltage accelerates the flowing electrons in n-type channel, and hence the hot-carriers possibly cause a serious damage near the drain region and deteriorate the source/drain (S/D) current. in this study, at high drain stress voltage, it appears that CLC TFT was degraded in the initial stress time (before 50 s), but the drain current was enhanced after 50 s. After 50 s stress time, the amount of grain boundary trap states near the drain side was getting large and the reflowing holes damaged the source region or injected into gate oxide near source side as well. (C) 2009 Elsevier Ltd. All rights reserved.