Browsing by Author "Chen, Te-Chih"

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Analysis of Anomalous Capacitance Induced by TAGIDL in p-Channel LTPS TFTs
(2010)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Li, Hung-Wei
;
Chen, Shih-Ching
In this work, a mechanism of anomalous capacitance in p-channel low temperature polycrystalline silicon thin film transistors (LTPS TFTs) was investigated. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between the gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measurement frequency and/or with increasing measurement temperature. By fitting the curve of the drain current vs electric field under off-state region, it was verified that the trap-assisted gate-induced drain leakage (TAGIDL) consists of the Pool-Frenkel emission and thermal field emission. In addition, the charge density calculated from the C(gsd)-V(g) measurement also has the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the TAGIDL. To suppress the anomalous capacitance, a band-to-band hot electron stress was utilized to reduce the vertical electric field between the gate and the drain. The electric field simulation was also performed by TCAD software. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3483759] All rights reserved.
Analysis of Degradation Mechanism in SONOS-TFT Under Hot-Carrier Operation
(2010-12-01)
Chen, Te-Chih
;
Chang, Ting-Chang
;
Chen, Shih-Ching
;
Hsieh, Tien-Yu
;
Jian, Fu-Yen
This letter investigates the degradation mechanism of polycrystalline silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon structure under OFF-state stress. During the electrical stress, the hot hole generated from band-to-band tunneling process will inject into gate dielectric, and the significant ON-state degradation (more than 1 order) indicates that the interface states are accompanied with hot-hole injection. In addition, the asymmetric I-V characteristics indicate that the interface states are located near the drain side. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Although both the vertical and lateral electrical fields are factors for degradation and hot-hole injection, the degradation is mainly affected by the lateral electrical field over a critical point.
Anomalous Capacitance Induced by GIDL in P-Channel LTPS TFTs
(2009-11-01)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Chen, Shih-Ching
;
Jian, Fu-Yen
In this letter, a mechanism of anomalous capacitance in p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) was investigated. In general, the effective capacitance was only the overlap region and independent with the frequency in LTPS TFTs under the OFF state. However, our experimental results reveal that the capacitance was related with the leakage current and that it was dependent with the measurement frequencies when operated at the OFF-state region. The increase of the capacitance value is verified to be due to the increase of the electron capacitance originating from a gate-induced drain-leakage (GIDL) one. Nevertheless, the GIDL-induced electron capacitance can be suppressed by employing band-to-band hot electron stress.
Anomalous on-current and subthreshold swing improvement in low-temperature polycrystalline-silicon thin-film transistors under Gate bias stress
(2011-03-21)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Jian, Fu-Yen
;
Li, Hung-Wei
This work investigates an improvement in anomalous on-current and subthreshold swing (SS) in Low-temperature polycrystalline-silicon thin-film transistors after positive gate bias stress. The experimental results reveal that the improved electric properties are due to the hole trapping at SiO(2) above the lightly doped drain regions, which causes a strong electric field at the gate corners. The effect of the hole trapping is to reduce the effective channel length and the SS. Besides, the stress-related electric field was also simulated by TCAD software to verify the mechanism above. (C) 2011 American Institute of Physics. [doi:10.1063/1.3568895]
Charge-Trapping-Induced Parasitic Capacitance and Resistance in SONOS TFTs Under Gate Bias Stress
(2011-03-01)
Lin, Chia-Sheng
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Chen, Ying-Chung
;
Chang, Ting-Chang
;
Jian, Fu-Yen
;
Li, Hung-Wei
This letter investigates the charge-trapping-induced parasitic resistance and capacitance in silicon-oxide-nitride-oxide-silicon thin-film transistors under positive and negative dc bias stresses. The results identify a parasitic capacitance in OFF-state C-V curve caused by electrons trapped in the gate insulator near the defined gate region during the positive stress, as well as the depletion induced by those trapped electrons. Meanwhile, the induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.
Degradation of Low Temperature Polycrystalline Silicon Thin Film Transistors under Negative Bias Temperature Instability Stress with Illumination Effect
(2010)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Li, Hung-Wei
;
Hsu, Wei-Che
This work investigates negative bias temperature instability (NBTI) in low temperature polycrystalline silicon thin film transistors (LTPS TFTs) in a darkened and in an illuminated environment of different light intensities. Experimental results reveal that the generations of interface state density (N(it)) are identical under various illuminated intensity NBTI stresses. Nevertheless, the degradation of the grain boundary trap (N(trap)) under illumination was more significant than that for the darkened environment, with degradation increasing as illumination intensity increases. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress. The increased N(trap) degradation leads to an increase in the darkened environment leakage current. This indicates that more traps are generated in the drain junction region than from carrier tunneling via the trap, resulting in leakage current. Conversely, an increase in N(trap) degradation results in a decrease in the photoleakage current. This indicates that the number of recombination centers increases in the poly-Si bulk, affecting photosensitivity in LTPS TFTs.
Illumination-Assisted Negative Bias Temperature Instability Degradation in Low Temperature Polycrystalline Silicon Thin-Film Transistors
(2009)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Hsu, Wei-Che
;
Chen, Shih-Ching
In this work, the negative bias temperature instability (NBTI) in low temperature polycrystalline silicon thin-film transistors in a darkened and in an illuminated environment was investigated. Experimental results reveal that the generation of interface state density (N(it)) showed no change between the different NBTI stresses. Nevertheless, the degradation of the grain boundary trap (N(trap)) under illumination was more significant than that in the darkened environment. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress.
Improvement in the bias stability of amorphous InGaZnO TFTs using an Al2O3 passivation layer
(2013-09-01)
Huang, Sheng-Yao
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Chang, Ting-Chang
;
Chen, Min-Chen
;
Chen, Te-Chih
;
Jian, Fu-Yen
This work presents the light-color-dependent negative bias stress (NBIS) effect on amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) with Al2O3 passivation layer. The colors of incident photon are varied from red to blue, that incident photon energies are all lower than the optical band gap of IGZO (3.2 eV). The experimental results show that the Al2O3 passivated devices present stable electrical behaviors under different incident lights (Delta V-T<0.1 V of dark and red, Delta V-T<1 V of green, and Delta V-T<4 V of blue), whereas the unpassivation devices exhibit observable negative shifts during NBIS (Delta V-T<1 V of dark and red, Delta V-T>8 V of green, and Delta V-T>15 V of blue). The degradation mechanism of the negative bias stress under illumination of a-IGZO TFTs is dominated by the photo-generated hole trapping at the gate insulator and/or interface between insulator and channel. In this result, the Al2O3 passivation layer can effectively passivate the defect in the a-IGZO film, reducing electron hole pair generated during the illumination processed. Crown Copyright (C) 2012 Published by Elsevier B.V. All rights reserved.
Investigating Degradation Behavior of InGaZnO Thin-Film Transistors induced by Charge-Trapping Effect under DC and AC Gate-Bias Stress
(2012)
Hsieh, Tien-Yu
;
Chang, Ting-Chang
;
Chen, Te-Chih
;
Tsai, Ming-Yen
;
Chen, Yu-Te
This paper investigates the degradation mechanism of amorphous InGaZnO thin-film transistors under DC and AC gate bias stress. Comparing the degradation behavior at equal accumulated effective stress time, more pronounced threshold voltage shift under AC positive gate bias stress in comparison with DC stress indicates extra electron-trapping phenomenon occurs in the duration of rising/falling time in pulse. Contrarily, illuminated AC negative gate bias stress exhibits much less threshold voltage shift than DC stress, which suggesting the photo-generated hole does not has sufficient time to drift to the interface of IGZO/gate insulator and causes hole-trapping under AC operation. Since the evolution of threshold voltage fits the stretched-exponential equation well, the different degradation tendencies under DC/AC stress can be attributed to the different electron-and hole-trapping efficiencies, and this is further verified by varying pulse waveform.
Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor
(2011-07-11)
Chen, Te-Chih
;
Chang, Ting-Chang
;
Hsieh, Tien-Yu
;
Lu, Wei-Siang
;
Jian, Fu-Yen
This letter investigates the degradation mechanism of amorphous indium-gallium-zinc oxide thin-film transistors under gate-bias stress. The larger V(t) shift under positive AC gate-bias stress when compared to DC operation indicates that an extra electron trapping mechanism occurs during rising/falling time during the AC pulse period. In contrast, the degradation behavior under illuminated negative gate-bias stress exhibits the opposite degradation tendency. Since electron and hole trapping are the dominant degradation mechanisms under positive and illuminated negative gate-bias stress, respectively, the different degradation tendencies under AC/DC operation can be attributed to the different trapping efficiency of electrons and holes. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3609873]
Investigation of gate-bias stress and hot-carrier stress-induced instability of InGaZnO thin-film transistors under different environments
(2013-09-01)
Hsieh, Tien-Yu
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Chang, Ting-Chang
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Chen, Te-Chih
;
Tsai, Ming-Yen
;
Chen, Yu-Te
This paper investigates the temperature and ambiance effects on various reliability issues for InGaZnO thin film transistors with an organic passivation layer. Hot-carrier stress and gate-bias stress are carried out under different environmental temperatures and ambient gases. The device exhibits relatively good stability under room temperture, whereas high temperature enhances degradation. Futhermore, different degradation behaviors after gate-bias stress in atmosphere and in vacuum can be attributed to gas adsorption/desorption-induced instability. Moreover, capacitance-voltage measurement techinique is utilized to analyze the degradation mechanism and to extract the density of state (DOS). The result reveals that the threshold voltage shift after both hot-carrier and gate-bias stress originates from the charge-trapping effect at the interface of gate insulator and active layer, with the extra trap states generated during stress responsible for C-V curve distortion. In addition, the asymmetric degradation behavior of gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs) indicates that trap states are generated near the drain side. (C) 2012 Elsevier B.V. All rights reserved.
Mechanism of a-IGZO TFT device deterioration-illumination light wavelength and substrate temperature effects
(2017-10-25)
Chen, Te-Chih
;
Kuo, Yue
;
Chang, Ting-Chang
;
Chen, Min-Chen
;
Chen, Hua-Mao
Device characteristics changes in an a-IGZO thin film transistor under light illumination and at raised temperature have been investigated. Light exposure causes a large leakage current, which is more obvious with an increase in the illumination energy, power and the temperature. The increase in the leakage current is due to the trap assisted photon excitation process that generates electron-hole pairs and the mechanism is enhanced with the additional thermal energy. The leakage current comes from the source side because holes generated in the process drift to the source side and therefore lower the barrier height. The above mechanism has been further verified with experiments of drain bias induced shifts in the threshold voltage and the subthreshold slope.
NBTI Degradation in LTPS TFTs Under Mechanical Tensile Strain
(2011-07-01)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Jian, Fu-Yen
;
Hsu, Wei-Che
This letter investigates the negative-bias temperature instability (NBTI) degradation of p-channel low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs) under mechanical tensile stress. Experimental results reveal that the interface state density N(it) and grain boundary trap density N(trap) of tensile-strained LTPS TFTs are more pronounced than those of unstrained LTPS TFTs. Extracted density of states and conduction activation energy E(a) both show increases due to the strained Si-Si bonds, which implies that strained Si-Si bonds are able to react with dissociated H during NBTI stress. Therefore, NBTI degradation is more significant after tensile strain than in an unstrained condition.
Stability of double gate amorphous In-Ga-Zn-O thin-film transistors with various top gate designs
(2017-12-01)
Chen, Te-Chih
;
Kuo, Yue
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Chang, Ting-Chang
;
Chen, Min-Chen
;
Chen, Hua-Mao
Electrical characteristics of the dual-gate amorphous indium gallium zinc oxide thin-film transistors have been studied. Compared with the traditional bottom gate thin film transistor, the dual-gate structure has a larger on-current and a smaller threshold voltage shift because of the formation of an additional carrier channel and the depletion of the semiconductor layer. The top gate-to-channel barrier height is critical to threshold voltage and the stability of the thin film transistor. The complete overlap between the top gate and the channel region is important for the top channel function, which warrants the large on-current and low threshold slope shift. Therefore, the top gate design is critical to the performance and stability of the dual-gate thin film transistor. (C) 2017 The Japan Society of Applied Physics
The suppressed negative bias illumination-induced instability in In-Ga-Zn-O thin film transistors with fringe field structure
(2012-11-26)
Chen, Yu-Chun
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Chang, Ting-Chang
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Li, Hung-Wei
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Hsieh, Tien-Yu
;
Chen, Te-Chih
This study investigates the suppressed negative gate bias illumination stress (NBIS) -induced instability of via-type amorphous indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) with fringe field (FF) structures. The less negative threshold voltage shifts of devices after NBIS are showed when device has larger FF structures. This finding is attributed to more dispersive distribution of photo-generated holes in the width direction of a-IGZO during NBIS, which reduce the hole trapping phenomenon in the front channel interface. The a-IGZO TFT with FF structure is expected to be an effective method to increase the electrical reliability of devices after NBIS. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4767996]
Transient Effect Assisted NBTI Degradation in p-Channel LTPS TFTs under Dynamic Stress
(2011)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Li, Hung-Wei
;
Chen, Shih-Ching
This work investigates dynamic negative bias temperature instability (NBTI) in p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) with different rise and fall times. Experimental results reveal identical increases in the interface state density (N(it)) induced by different dynamic NBTI stress conditions. Nevertheless, the degradation of the grain boundary trap (N(trap)) becomes more significant as rise time decreases to 1 mu s. Because the surface inversion layer cannot form during the short rise time, transient bulk voltage will cause excess holes to diffuse into the poly-Si bulk. Therefore, the significant N(trap) increase is assisted by this transient effect. (c) 2010 The Electrochemical Society. [DOI: 10.1149/1.3507253] All rights reserved.
Unusual Threshold Voltage Shift Caused by Self-Heating-Induced Charge Trapping Effect
(2010)
Jian, Fu-Yen
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Chang, Ting-Chang
;
Chu, An-Kuo
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Chen, Te-Chih
;
Chen, Shih-Ching
This article investigates the threshold voltage (V(t)) shift induced by a self-heating effect for n-channel low temperature poly-Si thin film transistors (TFTs) and finds that there is a shift of more than 3 V in the negative direction after a self-heating operation of 100 ms. The negative V(t) shift can be attributed to the charge-trapping effect caused by the holes generated by trap-assisted band-to-band thermionic field emission and trapped in the grain boundary of the poly-Si film substrate. We used lateral body contact structure to verify that this unusual V(t) shift is related to the holes trapped in the substrate. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3290686] All rights reserved.