Browsing by Author "Chen, Tien-Fu"

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A 0.48V 0.57nJ/Pixel Video-Recording SoC in 65nm CMOS
(2013-01-01)
Lin, Tay-Jyi
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Chien, Cheng-An
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Chang, Pei-Yao
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Chen, Ching-Wen
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Wang, Po-Hao
A 256b-Wordlength ReRAM-based TCAM with 1ns Search-Time and 14x Improvement in WordLength-EnergyEfficiency-Density Product using 2.5T1R cell
(2016)
Lin, Chien-Chen
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Hung, Jui-Yu
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Lin, Wen-Zhang
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Lo, Chieh-Pu
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Chiang, Yen-Ning
A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing
(2017-06-01)
Chang, Meng-Fan
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Lin, Chien-Chen
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Lee, Albert
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Chiang, Yen-Ning
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Kuo, Chia-Chen
Existing nonvolatile ternary content-addressable-memory (nvTCAM) suffers from limited word-length (WDL), large write-energy (E-W) and search-energy (E-S), and large cell area (A). This paper develops a 3T1R nvTCAM cell using a single multiple-level cell (MLC)-resistive RAM (ReRAM) device to achieve long WDL, lower E-W and E-S, and reduced cell area. Two peripheral control schemes were developed, dual-replica-row self-timed and invalid-entry power consumption suppression (IEPCS), for the suppression of dc current in 3T1R nvTCAM cells in order to reduce E-S. Two versions of the IEPCS scheme were developed (basic and charge-recycle-controlled) to alter the tradeoff between area overhead and power consumption in the updating of invalid-bits. A 128 b x 64 b 3T1R nvTCAM macro was fabricated using back-end-of-line ReRAM under 90-nm CMOS process. The fabricated MLC-based 3T1R nvTCAM macro achieved sub-1-ns search-delay and sub-6-ns wake-up time with supply voltage of 1 V and WDL = 64 b.
A 3T1R Nonvolatile TCAM Using MLC ReRAM with Sub-1ns Search Time
(2015-01-01)
Chang, Meng-Fan
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Lin, Chien-Chen
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Lee, Albert
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Kuo, Chia-Chen
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Yang, Geng-Hau
A Configurable Bus-Tracer for Error Reproduction in Post-Silicon Validation
(2013)
Chen, Shing-Yu
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Hsiao, Ming-Yi
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Jone, Wen-Ben
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Chen, Tien-Fu
;
交大名義發表
In today's modern system-on-chips (SoCs), there are several intellectual properties (IPs) on the system to provide different functionality. However, the more complex communications on SoCs are, the harder the programmer could discover all errors before first silicon during verification. Therefore, we provide a reconfigurable unit for recording the transactions between IPs and adopt logical vector clock [1] as timestamp of each trace. The programmable trigger unit (PTU) in debugging node (DN) could be configured by the validator to cache their interest sequences of transaction. Because the traces of transactions would have their own timestamp, during the post-silicon validation, we could reproduce the errors in faulty transactions between IPs and get more information for bypassing or fixing the problems. Furthermore, due to several entries of traces, which would shrink observation window very quickly, we also implement a compressor to compress traces before we store them into trace buffer. Finally, our experiments demonstrate that the proposed debugging architecture is capable of recording the critical transactions, and by the proposed reconfigurable debugging unit the debugging execution time can be reduced more than 80%.
A Configurable Bus-Tracer for Error Reproduction in Post-Silicon Validation
(2013-01-01)
Chen, Shing-Yu
;
Hsiao, Ming-Yi
;
Jone, Wen-Ben
;
Chen, Tien-Fu
;
交大名義發表
In today's modern system-on-chips (SoCs), there are several intellectual properties (IPs) on the system to provide different functionality. However, the more complex communications on SoCs are, the harder the programmer could discover all errors before first silicon during verification. Therefore, we provide a reconfigurable unit for recording the transactions between IPs and adopt logical vector clock [1] as timestamp of each trace. The programmable trigger unit (PTU) in debugging node (DN) could be configured by the validator to cache their interest sequences of transaction. Because the traces of transactions would have their own timestamp, during the post-silicon validation, we could reproduce the errors in faulty transactions between IPs and get more information for bypassing or fixing the problems. Furthermore, due to several entries of traces, which would shrink observation window very quickly, we also implement a compressor to compress traces before we store them into trace buffer. Finally, our experiments demonstrate that the proposed debugging architecture is capable of recording the critical transactions, and by the proposed reconfigurable debugging unit the debugging execution time can be reduced more than 80%.
A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata
(2017-12-01)
Tsai, Hsiang-Jen
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Chen, Chien-Chih
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Peng, Yin-Chi
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Tsao, Ya-Han
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Chiang, Yen-Ning
Regular expression matching becomes indispensable elements of Internet of Things network security. However, traditional ternary content addressable memory (TCAM) search engine is unable to handle patterns with wildcards, as it precisely tracks only one active state with single transition. This paper proposes a promising simultaneous pattern matching methodology for wildcard patterns by two separated engines to represent discrete finite automata. A key preprocessing to encode possible postfix pattern by a unique key ensures that follow-up patterns can accurately traverse all possible matches with limited hardware resources. This approach is practical and scalable for achieving good performance and low space consumption in network security, and it can be applicable to any regular expressions even with multiwildcard patterns. The experimental results demonstrate that this scheme can efficiently and accurately recognize wildcard patterns by simultaneously tracking only two active states. By adopting SRAM TCAM in the proposed architecture, the energy consumption is reduced to around 39%, compared with the energy consumption using a computing system that contains a large memory lookup and comparison overhead.
A Latency-Elastic and Fault-Tolerant Cache for Improving Performance and Reliability on Low Voltage Operation
(2015)
Yu, Yung-Hui
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Wang, Po-Han
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Tsai, Shang-Jen
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Chen, Tien-Fu
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資訊工程學系
The ever-increasing transistor threshold-voltage (Vth) variation caused by process technologies shrink brings the performance and reliability issues in SRAM cells. To keep power limitations, scaling down the supply voltage is inevitable in mobile devices and future chips. However, caches become susceptible even fail in low voltages, and the distribution of access latencies increases in new technology nodes. To deal with the respectable power of SRAM in modern processors, the memory reliability wall poses a major challenge in cache design nowadays and continues for years to come. This thesis proposes a latency-elastic and fault-tolerant cache not only for fault tolerant, but aiming at the performance issues. It varies the latency of cache access to achieve better-than-worst-case designs for improving performance.
A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing
(2016-11)
Chang, Meng-Fan
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Huang, Lie-Yue
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Lin, Wen-Zhang
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Chiang, Yen-Ning
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Kuo, Chia-Chen
This paper outlines the RC-filtered stress-decoupled (RCSD) 4T2R nonvolatile TCAM (nvTCAM) with the following benefits: 1) reduced NVM-stress; 2) reduced ML parasitic load; and 3) suppression of match-line (ML) leakage current from match cells. The RCSD-4T2R cell achieves a 6x reduction in NVM-stress, a 2x increase in maximum wordlength, and a 2x reduction in search delay. In this paper, we also outline two search schemes, referred to as dynamic source-line pulse controlled (DSL-PC) search and dataline-pulse controlled (DL-PC) search, which were developed specifically for the RCSD-4T2R nvTCAM. We fabricated a 128 x 32 b RCSD-4T2R nvTCAM macro with HfO ReRAM using a 180 nm CMOS process. Using the DSL-PC and DL-PC schemes, the measured search delay of the RCSD-4T2R nvTCAM macro was 1.2 ns under typical VDD.
A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100x for Storage Class Memory Applications
(2017-01)
Khwa, Win-San
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Chang, Meng-Fan
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Wu, Jau-Yi
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Lee, Ming-Hsiu
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Su, Tzu-Hsiang
For multilevel cell (MLC) phase change memory (PCM), resistance drift ( R-drift) phenomenon causes cell resistance to increase with time, even at room temperature. As a result, the fixed-threshold-retention (FTR) raw-bit-error-rate (RBER) surpasses practical ECC correction ability within hours after being programmed. This study proposes a resistance drift compensation (RDC) scheme to mitigate R-drift issue. The proposed RDC scheme realizes PCM drift compensation and features RDC pulse to suppress ECC decoding failure. The proposed approach was validated using a 90-nm 128M cells PCM chip and an FPGA-based memory controller verification system. The MLC PCM FTR RBER has been suppressed by over 100x, thereby bringing it within ECC capability. The effectiveness of the RDC scheme was verified up to 106 cycles.
A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100x for Storage Class Memory Applications
(2017-01)
Khwa, Win-San
;
Chang, Meng-Fan
;
Wu, Jau-Yi
;
Lee, Ming-Hsiu
;
Su, Tzu-Hsiang
For multilevel cell (MLC) phase change memory (PCM), resistance drift ( R-drift) phenomenon causes cell resistance to increase with time, even at room temperature. As a result, the fixed-threshold-retention (FTR) raw-bit-error-rate (RBER) surpasses practical ECC correction ability within hours after being programmed. This study proposes a resistance drift compensation (RDC) scheme to mitigate R-drift issue. The proposed RDC scheme realizes PCM drift compensation and features RDC pulse to suppress ECC decoding failure. The proposed approach was validated using a 90-nm 128M cells PCM chip and an FPGA-based memory controller verification system. The MLC PCM FTR RBER has been suppressed by over 100x, thereby bringing it within ECC capability. The effectiveness of the RDC scheme was verified up to 106 cycles.
A Resistance-Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100x for Storage-Class Memory Applications
(2016)
Khwa, Win-San
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Chang, Meng-Fan
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Wu, Jau-Yi
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Lee, Ming-Hsiu
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Su, Tzu-Hsiang
A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security
(2012-05-01)
Cheng, Chieh-Jen
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Wang, Chao-Ching
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Ku, Wei-Chun
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Chen, Tien-Fu
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Wang, Jinn-Shyan
Contemporary network security applications generally require the ability to perform powerful pattern matching to protect against attacks such as viruses and spam. Traditional hardware solutions are intended for firewall routers. However, the solutions in the literature for firewalls are not scalable, and they do not address the difficulty of an antivirus with an ever-larger pattern set. The goal of this work is to provide a systematic virus detection hardware solution for network security for embedded systems. Instead of placing entire matching patterns on a chip, our solution is a two-phase dictionary-based antivirus processor that works by condensing as much of the important filtering information as possible onto a chip and infrequently accessing off-chip data to make the matching mechanism scalable to large pattern sets. In the first stage, the filtering engine can filter out more than 93.1% of data as safe, using a merged shift table. Only 6.9% or less of potentially unsafe data must be precisely checked in the second stage by the exact-matching engine from off-chip memory. To reduce the impact of the memory gap, we also propose three enhancement algorithms to improve performance: 1) a skipping algorithm; 2) a cache method; and 3) a prefetching mechanism.
Accelerating Full-System Simulation and App Analysis through Focused Multi-Granularity Profiling
(2014)
Su, Tzu-Hsiang
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Wu, Wei-Shan
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Chou, Chen-Te
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Cheng, Yuan-Chun
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Tsai, Meng-Ting
Faced with the rapid divergence of hardware used on embedded devices, there is a need for a tool that can efficiently assist with hardware/software co-design and architecture verification. Speeding up those ESL phases greatly reduces the length of development periods. To address this issue, our work implements a novel multi-granularity tracer for Android\'s simulator to provide ESL hardware design performance analysis and verification. In addition, we propose a flexible ESL module interface for system hardware designers to explore new hardware components via simple modules. Our work also enables software developers to identify performance bottleneck and assess software performance of new hardware components. Our case studies and experimental results show that our multi-granularity Android tracer can strip away irrelevant information to shave time off the architecture development period.
Accelerating Manycore Simulation by Efficient NoC Interconnection Partition on FPGA Simulation Platform
(2011)
Ku, Wei-Chun
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Chen, Tien-Fu
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交大名義發表
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National Chiao Tung University
manycore architecture is the trend of system design. However, manycore simulators face the important issue than general multicore simulators is simulation speed. Several studies provide a FPGA simulation methodology to solve it, but they almost do it by providing a new internal design of core. And some of them don\'t care the correctness without interconnection simulation. This paper provides a PVCT module and NIP methodology to solve these two issues. According to our experiment, we could provide a 91.4 MIPS simulation performance averagely with Splash2 benchmark by three physical cores. The number of three is decided by capability of Xilinx XC2V8000 FPGA chip.
Accelerating R Data Analytics in IoT Edge Systems by Memory Optimization
(2017-01-01)
Liou, De-Yin
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Chen, Chien-Chih
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Chen, Tien-Fu
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Lin, Tay-Jyi
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資訊工程學系
With the number and variety of IoT devices increasing, a large amount of data have to be moved to the cloud, resulting into unpredictable latency from limitation of network bandwidth. R language, the most popular analytic tool, has a serious bottleneck, memory garbage collection, which will become even worse problem at the edge systems with limited memory resources. Processing a large amount of dynamic objects and high percentage of LLC misses with significantmiss penalty are the two key issues in the R execution environment. In this paper, we propose a Partially Parallel Garbage Collection to improve the waiting time during garbage collection; and a centralized memory allocation mechanism to reduce miss penalty that is caused by the high percentage of LLC misses. Our optimizations can bring benefits to those machine learning algorithms that spend most of time in R for processing large data list at the edge systems.
Adaptive Granularity and Coordinated Management for Timely Prefetching in Multi-Core Systems
(2015)
Chang, Chia-Jung
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Peng, Yin-Chi
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Chen, Chien-Chih
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Chen, Tien-Fu
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Yew, Pen-Chung
For the last decade, there have been varying techniques for hardware prefetching to improve the system performance. However, untimely prefetching may pollution caches and resulting into significant performance degradation. In this work, we introduce an Adaptive Granularity and coordinated Prefetching (AGP) that consists of a coarse-grained and fine-grained prefetched mechanism to provide a better caching environment for parallel applications. AGP targets on the degree-adjusting and location-choosing and tries to minimize the influence caused by prefetcher for each core. AGP could produce more timely prefetched requests reducing the cache pollutions and contentions. Across a variety of PARSEC benchmarks, AGP can contribute 6.5% (up to 36%) of performance improvement on a 4-core multicore system compared to the non-prefetching.
Adaptive Variable-Latency Cache Management for Low-Voltage Caches
(2014-01-01)
Yu, Yung-Hui
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Wang, Po-Hao
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Chen, Tien-Fu
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Lin, Tay-Jyi
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Wang, Jinn-Shyan
Scaling down the supply voltage for embedded SoC becomes a necessary technique to lower power requirements in mobile devices. However, caches become susceptible or even fail in low voltages, and distribution of access latencies is significantly increased in new technology nodes. Past researches suggested several solutions to deal with the memory reliability at low voltages, where a timing table records cache lines with latency faults. This paper proposes cache management strategies for variable-latency caches at low voltages. We analyze the locality effect and propose two methods to dynamically adapt latency faults at run time and give the advantages of those methods compared to traditional LRU for low-voltage caches.
Cross-Layer Dynamic Prefetching Allocation Strategies for High-Performance Multicores
(2013)
Peng, Yin-Chi
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Chen, Chien-Chih
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Chang, Chia-Jung
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Chen, Tien-Fu
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Yew, Pen-Chung
For the last decade, there have been varying techniques for hardware prefetchers to improve the system performance. However, due to limited space and bandwidth in a multicore system, the prefetching data fetched by prefetcher may pollute L1 cache even though the data is useful, thus resulting into significant performance degradation. Most contemporary multicore systems simply disable prefetching to avoid unexpected contention. This paper proposes a cross-layer and dynamic Prefetch Allocation Management (PAM) to provide better caching strategies in a parallel environment. Our approach has two main mechanisms, targeting at the different prefetch degree and location choices to minimize the cache pollution and contention. Across a variety of SPLASH2 and PARSEC benchmark, our PAM approach can contribute up to 12% of performance improvement on a 4-core multicore system compared to the static prefetcher configuration and also saves 9.1% of the memory bandwidth consumption of memory system.
Cross-Layer Dynamic Prefetching Allocation Strategies for High-Performance Multicores
(2013-01-01)
Peng, Yin-Chi
;
Chen, Chien-Chih
;
Chang, Chia-Jung
;
Chen, Tien-Fu
;
Yew, Pen-Chung
For the last decade, there have been varying techniques for hardware prefetchers to improve the system performance. However, due to limited space and bandwidth in a multicore system, the prefetching data fetched by prefetcher may pollute L1 cache even though the data is useful, thus resulting into significant performance degradation. Most contemporary multicore systems simply disable prefetching to avoid unexpected contention. This paper proposes a cross-layer and dynamic Prefetch Allocation Management (PAM) to provide better caching strategies in a parallel environment. Our approach has two main mechanisms, targeting at the different prefetch degree and location choices to minimize the cache pollution and contention. Across a variety of SPLASH2 and PARSEC benchmark, our PAM approach can contribute up to 12% of performance improvement on a 4-core multicore system compared to the static prefetcher configuration and also saves 9.1% of the memory bandwidth consumption of memory system.