Browsing by Author "Chen, Tsan-Jieh"

Now showing 1 - 14 of 14

A 0.5V 1.27mW Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia
(2014-01-01)
Tang, Kea-Tiong
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Chiu, Shih-Wen
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Shih, Chung-Hung
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Chang, Chia-Ling
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Yang, Chia-Min
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control
(2014-01-01)
Chen, Wei-Ming
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Chiueh, Herming
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Chen, Tsan-Jieh
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Ho, Chia-Lun
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Jeng, Chi
An 8-channel closed-loop neural-prosthetic SoC is presented for real-time intracranial EEG (iEEG) acquisition, seizure detection, and electrical stimulation in order to suppress epileptic seizures. The SoC is composed of eight energy-efficient analog front-end amplifiers (AFEAs), a 10-b delta-modulated SAR ADC (DMSAR ADC), a configurable bio-signal processor (BSP), and an adaptive high-voltage-tolerant stimulator. A wire-less power-and-data transmission system is also embedded. By leveraging T-connected pseudo-resistors, the high-pass (low-pass) cutoff frequency of the AFEAs can be adjusted from 0.1 to 10 Hz (0.8 to 7 kHz). The noise-efficiency factor (NEF) of the AFEA is 1.77, and the DMSAR ADC achieves an ENOB of 9.57 bits. The BSP extracts the epileptic features from time-domain entropy and frequency spectrum for seizure detection. A constant 30-mu A stimulus current is delivered by closed-loop control. The acquired signals are transmitted with on-off keying (OOK) modulation at 4 Mbps over the MedRadio band for monitoring. A multi-LDO topology is adopted to mitigate the interferences across different power domains. The proposed SoC is fabricated in 0.18-mu m CMOS and occupies 13.47 mm(2). Verified on Long Evans rats, the proposed SoC dissipates 2.8 mW and achieves high detection accuracy 92% within 0.8 s.
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic SoC for Real-Time Epileptic Seizure Control
(2013-01-01)
Chen, Wei-Ming
;
Chiueh, Herming
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Chen, Tsan-Jieh
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Ho, Chia-Lun
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Jeng, Chi
A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia
(2014-12-01)
Chiu, Shih-Wen
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Wang, Jen-Huo
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Chang, Kwuang-Han
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Chang, Ting-Hau
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Wang, Chia-Min
Ventilator-associated pneumonia (VAP) still lacks a rapid diagnostic strategy. This study proposes installing a nose-on-a-chip at the proximal end of an expiratory circuit of a ventilator to monitor and to detect metabolite of pneumonia in the early stage. The nose-on-a-chip was designed and fabricated in a 90-nm 1P9M CMOS technology in order to downsize the gas detection system. The chip has eight on-chip sensors, an adaptive interface, a successive approximation analog-to-digital converter (SAR ADC), a learning kernel of continuous restricted Boltzmann machine (CRBM), and a RISC-core with low-voltage SRAM. The functionality of VAP identification was verified using clinical data. In total, 76 samples infected with pneumonia (19 Klebsiella, 25 Pseudomonas aeruginosa, 16 Staphylococcus aureus, and 16 Candida) and 41 uninfected samples were collected as the experimental group and the control group, respectively. The results revealed a very high VAP identification rate at 94.06% for identifying healthy and infected patients. A 100% accuracy to identify the microorganisms of Klebsiella, Pseudomonas aeruginosa, Staphylococcus aureus, and Candida from VAP infected patients was achieved. This chip only consumes 1.27 mW at a 0.5 V supply voltage. This work provides a promising solution for the long-term unresolved rapid VAP diagnostic problem.
A Hardware Implementation of Real-Time Epileptic Seizure Detector on FPGA
(2011)
Chen, Tsan-Jieh
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Jeng, Chi
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Chang, Shun-Ting
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Chiueh, Herming
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Liang, Sheng-Fu
a considerable portion of epilepsy cannot be well treated by today\'s available therapies. Brain stimulation with closed-loop seizure control was recently proposed. In our previous work, high accuracy of seizure controller (92-99% during wake-sleep states) using a microcontroller has been proposed and implemented to verify functionality of seizure detection and suppression on a freely moving rat. In this paper, the soft intellectual property (IP) of epileptic seizure detector in the implantable system on chip (SoC) for epileptic seizure control is proposed to achieve continuous real-time processing and low power consumption. All the essential macros for epileptic seizure detector are implemented and integrated in field programmable gate array (FPGA) to verify functionality and capability. The evaluation results of the prototype supported possible application of a portable and continuous real-time seizure control.
A Multi-Channel Multi-Mode Physiological Signals Acquisition and Analysis Platform
(2013)
Lee, Sheng-Cheng
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Chen, Tsan-Jieh
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Chiueh, Herming
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
With the recent evolution of medical device developments, physiological signal acquisition system is widely used in health monitoring, brain machine interface, and neural prosthesis, etc. In this paper, a multi-channel multi-mode biomedical signal acquisition and analysis platform is designed and implanted. The platform includes a customized low-distortion, high signal-to-noise ratio (SNR) analog to digital converter (ADC), and a field-programmable gate array (FPGA) with an embedded soft-core of 32-bit RISC processor. A multi-mode ADC was developed to meet the resolution and bandwidth requirement of different physiological signals. The soft-core and its corresponding software was designed and implemented to provide a versatile platform for different bio-medical applications. The integration of multi-mode data converter and signal processing platform enable the turnkey solution to develop different bio-medical applications such as on-line seizure detection, heart rate monitor, physiological signals recorder, etc.
An Image Combiner and Acquisition Interface for Space Remote Sensing Applications
(2009)
Chen, Tsan-Jieh
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Chiueh, Herming
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Tsai, Hann-Huei
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Chiu, Chin-Fong
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電子工程學系及電子研究所
high resolution image combination and processing plays an important role in today's satellites' remote sensing applications. This paper presents an image recombination and processing circuitries (ICAI) for one-dimensional multi-strip CMOS image sensors. The proposed system take advantage of the satellites' linear moving property to control the expose time of CMOS image sensor and provides the realtime ability to continuous generate 12,000 x N high-resolution image for space remote sensing applications. The ICAI chip contains an image sensor control logics, image combiner, and host interface, one-dimensional pixel is combined to form a two-dimensional image by proposed circuitry. A prototype chip of ICAI was designed and fabricated with TSMC 0.18 mu m CMOS 1 P6M technology. The die size is 2.91 mm by 2.91 mm, and the power consumption is 20 mW operating at 8MHz under a 1.8 V supply voltage.
Hardware-Efficient EVD Processor Architecture in FastICA for Epileptic Seizure Detection
(2012)
Shih, Yi-Hsin
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Chen, Tsan-Jieh
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Yang, Chia-Hsiang
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Chiueh, Herming
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交大名義發表
Independent component analysis (ICA) is a key signal processing technique to improve the detection accuracy of epileptic seizures. It separate artifacts and epileptic signals, which facilitates the succeeding signal processing for seizure detection. FastICA is an efficient algorithm to compute ICA through proper pre-processing. In the preprocessing stage of the FastICA, eigenvalue decomposition (EVD) is applied to reduce the convergence time of iterative calculation of weights for demultiplexing received multi-channel signals. To calculate EVD efficiently, the Jacobi method is preferable since an array structure is proposed to decompose matrix efficiently by leveraging givens rotations. Multiple diagonal and off-diagonal processing elements run in parallel to calculate EVD. The micro-rotations can be realized efficiently by coordinate rotation digital computer (CORDIC), which calculates trigonometric functions using only addition, shift, and table lookup without dedicated multipliers. In this work, an approximate Jacobi method is adopted instead to reduce the number of iterations significantly. Optimized rotation angles can be calculated efficiently using shift-add operations for multiplications with coefficients of power of 2 in the diagonal processing elements. Normalization operation in the original mathematical formulation can be omitted due to signal re-scaling in both diagonal and off-diagonal processing elements. The number of processing cycles is reduced by 6 times for each sweep due to the reduced number of pipelining stages in the critical path. The approximate Jacobi method provides a 6x speedup (185-252 cycles instead of 1440 cycles) for a 6-channel EVD. An overall 77.2% area reduction is achieved due to arithmetic simplification and hardware reduction. The hardware architecture is verified by testing the human electroencephalogram (EEG) signals from the Freiburg Seizure Prediction EEG (FSPEEG) database.
High Definition Image Pre-Processing System for Multi-Stripe Satellites' Image Sensors
(2012-09-01)
Chen, Tsan-Jieh
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Chiueh, Herming
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Hsieh, Chih-Cheng
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Yin, Chin
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Chang, Wen-Hsu
"High-resolution image sensors play an important role in today's satellites' remote sensing applications. This paper presents an image recombination and processing system for one-dimensional multi-strip complementary metal-oxide semiconductor image sensors (CISs.) The proposed system takes advantage of the satellites' linear moving property to control the exposure time of CIS and provides the real-time ability to generate 11 200 x N high-resolution images for satellites' remote sensing. Using hardware accelerators coupled with versatile microprocessors, the architecture is able to offer processing capability as well as long-term maintainability for space-borne platforms. The details of hardware design to meet real-time requirement are presented. The prototype, which contains four strip CISs and field programmable gate array-based prototyping, was implemented to verify functionality and capability of real-time image acquisition and combination. The implementation results show that it is feasible to integrate the proposed system into a single chip."
Live Demonstration: A Multi-Channel ECoG Acquisition SoC for Real-Time Seizure Detection
(2012)
Chen, Tsan-Jieh
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Lee, Sheng-Cheng
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Chiueh, Herming
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
Live Demonstration: The Prototype of Real-Time Image Pre-Processing System for Satellites' Remote Sensing
(2011)
Chen, Tsan-Jieh
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Weng, Chih-Hui
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Chiueh, Herming
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Hsieh, Chih-Cheng
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Yeh, Shang-Fu
the live demonstration shows the prototype of image recombination and processing system for one-dimensional multi-strip CMOS image sensors (CISs.) The proposed final system is discussed in the main paper, which takes advantage of the satellites' linear moving property to control the exposure time of CIS and provides the real-time ability to generate 11,200 x N high-resolution image for satellites' remote sensing applications. The prototype, which contains four strip CISs, is implemented to verify functionality and capability of real-time image acquisition and combination. The implementation result shows the proposed system, which demands four times larger throughput than the prototype, is feasible in a chip.
The Implementation of a Low-Power Biomedical Signal Processor for Real-Time Epileptic Seizure Detection on Absence Animal Models
(2011-12-01)
Chen, Tsan-Jieh
;
Chiueh, Herming
;
Liang, Sheng-Fu
;
Chang, Shun-Ting
;
Jeng, Chi
Epilepsy is one of the most common neurological disorders, with a worldwide prevalence of approximately 1%. A considerable portion of epilepsy patients cannot be treated sufficiently by today's available therapies. Implantable closed-loop neurostimulation is an innovative and effective method for seizure control. A real-time seizure detector is the kernel of a closed-loop seizure controller. In this paper, a low-power biomedical signal processor based on reduced instruction set computer (RISC) architecture for real-time seizure detection is implemented to achieve low-power consumption and perform continuous and real-time processing. The low-power processor is implemented in a 0.18 mu m complementary-metal-oxide semiconductor technology to verify functionality and capability. The measurement results show the implemented processor can reduce over 90% power consumption compared with our previous prototype, which was implemented on an enhanced 8051 microprocessor. This seizure detector was applied to the continuous EEG signals of four Long-Evans rats with spontaneous absence seizures. It also processed 24 h long-term and uninterrupted EEG sequence. The developed seizure detector can be applied for online seizure monitoring and integrated with an electrical stimulator to perform a closed-loop seizure controller in the future.
The Implementation of a Low-Power Biomedical Signal Processor for Real-Time Epileptic Seizure Detection on Absence Animal Models
(2011-12-01)
Chen, Tsan-Jieh
;
Chiueh, Herming
;
Liang, Sheng-Fu
;
Chang, Shun-Ting
;
Jeng, Chi
Epilepsy is one of the most common neurological disorders, with a worldwide prevalence of approximately 1%. A considerable portion of epilepsy patients cannot be treated sufficiently by today\'s available therapies. Implantable closed-loop neurostimulation is an innovative and effective method for seizure control. A real-time seizure detector is the kernel of a closed-loop seizure controller. In this paper, a low-power biomedical signal processor based on reduced instruction set computer (RISC) architecture for real-time seizure detection is implemented to achieve low-power consumption and perform continuous and real-time processing. The low-power processor is implemented in a 0.18 mu m complementary-metal-oxide semiconductor technology to verify functionality and capability. The measurement results show the implemented processor can reduce over 90% power consumption compared with our previous prototype, which was implemented on an enhanced 8051 microprocessor. This seizure detector was applied to the continuous EEG signals of four Long-Evans rats with spontaneous absence seizures. It also processed 24 h long-term and uninterrupted EEG sequence. The developed seizure detector can be applied for online seizure monitoring and integrated with an electrical stimulator to perform a closed-loop seizure controller in the future.
The Prototype of Real-Time Image Pre-Processing System for Satellites' Remote Sensing
(2011)
Chen, Tsan-Jieh
;
Weng, Chih-Hui
;
Chiueh, Herming
;
Hsieh, Chih-Cheng
;
Yeh, Shang-Fu
high resolution image combination and processing plays an important role in today's satellites' remote sensing applications. This paper presents an image recombination and processing system for one-dimensional multi-strip CMOS image sensors (CISs.) The proposed system takes advantage of the satellites' linear moving property to control the exposure time of CIS and provides the real-time ability to generate 11,200 x N high-resolution image for satellites' remote sensing applications. The details of hardware design to meet real-time requirement are given out. The prototype, which contains four strip CISs, is implemented to verify functionality and capability of real-time image acquisition and combination. The implementation results show the proposed system, which demands four times larger throughput than the prototype, is feasible in a chip.