Browsing by Author "Chen, Tsan-Wen"

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A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications
(2009-11-01)
Chen, Tsan-Wen
;
Yu, Jui-Yuan
;
Yu, Chien-Ying
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
This work provides a dual-mode baseband transceiver chipset for wireless body area network (WBAN) system. The modulation schemes include multi-tone code division multiple access (MT-CDMA) and orthogonal frequency division multiplexing (OFDM) to meet multi-user coexistence (up to 8) and high data rate purposes. Based on the analysis of the WBAN operation behavior, several methods including higher data rate, optimal storage determination, and low power implementation techniques are proposed to reduce the transmission energy. To achieve tiny area integration, an embedded phase frequency tunable clock generator and frequency error pre-calibration scheme are provided to extend the frequency mismatch tolerance to 100 ppm (2.5x of state-of-the-art systems). This chipset is manufactured in 90 nm standard CMOS process. Working at supply voltage of 0.5 V, this chipset is able to provide maximum date rate of 4.85 Mbps with modulator power consumption of 5.52 W.
A 0.5V 4.85Mbps Dual-Mode Baseband Transceiver with Extended Frequency Calibration for Biotelemetry Applications
(2008)
Yu, Jui-Yuan
;
Yu, Chien-Ying
;
Huang, Shang-Bin
;
Chen, Tsan-Wen
;
Chen, Juinn-Ting
This work provides a dual-mode transceiver chipset for wireless body area network (WBAN). The modulation schemes include both MT-CDMA and OFDM. A phase-frequency tunable clock generator (PFTCG) is designed with frequency and phase tuning capability on the fly. A rotator-and-synthesizer driven (RSD) frequency pre-calibration with the aid of the PFTCG enables calibration for extended 100ppm frequency error (2.5x of state-of-the-art systems). This chip is manufactured in 90nm standard CMOS process. The supply voltage to the chip core is globally applied at 0.5V with 12 power- and voltage-domain partitions for sleep-active and voltage-scaling management. The PFTCG is operated at 5MHz with RMS jitter 145ps. The transceiver chipset provides maximum 4.85Mbps data rate with 73.7% power reduction in baseband circuit processing.
A LOW-POWER ALL-DIGITAL PHASE MODULATOR PAIR FOR LINC TRANSMITTERS
(2011)
Tsai, Ping-Yuan
;
Chen, Tsan-Wen
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a low-power all-digital phase modulator (PM) pair to generate constant-envelope signals for LINC transmitters. To reduce the power overhead, an open-loop delay line based phase shifter with a continuous locking scheme is adopted for the PM design. This design is implemented by 90 nm CMOS technology with active area of 0.1892 mm(2). The PM provides 8-bit resolution with RMS error 0.33 degrees at IF frequency 80 MHz, and the power consumption is only 885 uW with 1.0 V supply voltage. Considering a 64-QAM OFDM system, the EVM of -31.87 dB can be achieved by using the proposed PM pair.
A QPSK/16-QAM OFDM-based 29.1Mbps LINC Transmitter for Body Channel Communication
(2012)
Tsai, Ping-Yuan
;
Hsu, Shu-Yu
;
Chang, Jen-Shin
;
Chen, Tsan-Wen
;
Lee, Chen-Yi
This paper proposed a high speed Body Channel Communication (BCC) transmitter under IF 20MHz, adopting the OFDM modulation and uneven multi-level LINC technique to reduce the power and complexity of the front-end circuit. The OFDM uses 16-QAM modulation to enhance the data rate and could select to use a convolutional code to increase the coding gain. The phase modulator in the LInear amplification with Nonlinear Component (LINC) transmitter uses not only clock-gating scheme but also the glitch free protection. A detection and calibration DSP are also integrated to solve the LINC branch mismatch problem. Finally the capacitive sensing circuit provides the information of the connectivity between pastes and human. The chip is implemented by 90nm CMOS process, with die area 1.3mm(2). The maximum data rate could achieve 29.1Mbps. The total power is 1.925mW, resulting in 0.07nJ/bit transmission energy and 2.92 bps/Hz spectral efficiency.
A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters
(2011-11-01)
Chen, Tsan-Wen
;
Tsai, Ping-Yuan
;
Yu, Jui-Yuan
;
Lee, Chen-Yi
;
電機工程學系
Linear amplification with nonlinear components (LINC) is an attractive technique for achieving linear amplification with high efficiency. This paper presents a sub-mW all-digital signal component separator (SCS) design for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. In addition, a digital mismatch compensation scheme is proposed and integrated into the SCS to reduce the design complexity of the power amplifier. This chip is manufactured in a 90 nm standard CMOS process with an active area of 0.06 mm(2). The DCPS can generate phase-modulated signals at 100 MHz with 8-bit resolution and RMS error 9.33 ps (0.34 degrees). The phase calculation can be performed at a maximum speed of 50 MHz using a 0.5 V supply voltage, resulting in a 73.88% power reduction. Comparing to state-of-the-art, the power consumption of the overall SCS is only 949.5 mu W which minimizes the power overhead for an LINC transmitter. This SCS with the branch mismatch compensation provides a 0.02 dB gain and 0.15 degrees phase fine-tune resolution without adding additional front-end circuits. Considering 1 dB gain and 10 degrees phase mismatch, the system EVM of -29.81 dB and ACPR of -34.56 dB can still be achieved for 5 MHz bandwidth 64-QAM OFDM signals.
An Energy-Efficient OFDM-Based Baseband Transceiver Design for Ubiquitous Healthcare Monitoring Applications
(2011)
Shih, Tzu-Chun
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Chen, Tsan-Wen
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Sung, Wei-Hao
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Tsai, Ping-Yuan
;
Lee, Chen-Yi
This work proposes an orthogonal frequency division multiplexing (OFDM) based baseband transceiver design for wireless body area network (WBAN) application. Based on the analysis of the WBAN operation behavior, high transmission data rate and low power implementation techniques are proposed to reduce the transmission energy. An electrocardiography (ECG) transmission platform is also established with proposed design for system evaluation. This chip is implemented in a 90nm CMOS technology with the core size of 2.85 mm(2), and this baseband transceiver dissipates 357.14 uW with supply voltage 0.5 V. The proposed chip provides maximum 9.7 Mbps data rate, resulting in active duty cycle of 0.1763% and the transmission energy of 0.37 nJ / bit.
Second-Order Statistics Based Prefilter-Blind Equalization for MIMO-OFDM
(2008)
Kuo, Kuan-Ling
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Chen, Tsan-Wen
;
Fung, Carrson C.
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
In this paper, a SOS-based prefilter-blind equalizer for MIMO-OFDM system which can equalize FIR-MIMO channel at the receiver is proposed. The proposed scheme uses a set of orthogonal prefilters at the transmitter such that the transmitted signal can be colored temporally thereby satisfying the identifiability condition previously proposed by Hua and Tugnait. The scheme is shown to outperform previously proposed schemes in terms of BER and computational complexity. Simulation results have shown that the BER performance is close to that of a least-squares zero-forcing equalizer with perfect channel knowledge.