Browsing by Author "Chen, Tung-Hung"

Now showing 1 - 2 of 2

A thick CESL stressed ultra-small (Lg=40nm) SiGe-channel MOSFET fabricated with 193nm scanner lithography and TEOS hard mask etching
(2007-01-01)
Liao, Wen-Shiang
;
Chen, Tung-Hung
;
Lin, Hsin-Hung
;
Chang, Wen-Tung
;
材料科學與工程學系
A 100 angstrom-thick SiGe (22.5%) channel MOSFET with gate length down to 40nm has been successfully integrated with 14 angstrom nitrided gate oxide as well as a 1200 angstrom high-compressive PECVD ILD-SiNx stressing layer as the contact etching stop layer (CESL) that enhances the PMOS electron mobility with +33% current gain. To achieve a poly-Si gate length target of 400 angstrom (40nm), a 193nm scanner lithography and an aggressive oxide hard mask etching techniques were used. First, a 500 angstrom-thick TEOS hard mask layer was deposited upon the 1500 angstrom A-thick poly-Si gate electrode. Second, both 1050 angstrom-thick bottom anti-reflective coating (BARC) and 2650 angstrom-thick photoresist (P/R) were coated and a 193nm scanner lithography tool was used for the gate layout patterning with nominal logic 90nm exposure energy. Then, a deep sub-micron plasma etcher was used for an aggressive P/R and BARC trimming down processing and the TEOS hard mask was subsequently plasma etched in another etching chamber without breaking the plasma etcher's vacuum. Continuously, the P/R and BARC were removed with a plasma ashing and RCA cleaning. Moreover, the patterned Si-fin capping oxide can be further trimmed down with a diluted HF(aq) solution (DHF) while rendering the RCA cleaning process and the remained TEOS hard mask is still thick enough for the subsequent poly-Si gate main etching. Finally, an ultra narrow poly-Si gate length of 40nm with promising PMOS drive current enhancement can be formed through a second poly-Si etching, which is above the underneath SiGe (22.5%) conduction channel as well as its upper 14 angstrom-thick nitrided gate oxide.
A thin FinFET Si-fin body structure fabricated with 193nm scanner photolithography and composite hard mask etching technique upon bulk-Si substrate
(2007-01-01)
Liao, Wen-Shiang
;
Liu, Yu-Huan
;
Chang, Wen-Tung
;
Chen, Tung-Hung
;
Shih, Tommy
A thin FinFET bulk Si-fin body structure has been successfully fabricated upon bulk-Si wafers through using 193nm scanner lithography and a composite hard mask etching technique. First, a 100 angstrom-thick buffer SiO2 layer was thermally grown upon the bulk silicon layer and subsequently a 1200 angstrom-thick SiNx layer and a 1000 angstrom-thick TEOS SiO2 hard mask layer was chemically vapor deposited to form a composite hard mask structure of buffer-SiO2/SiNx/TEOS. Second, both 1050 angstrom-thick BARC and 2650 angstrom-thick photoresist (P/R) were coated and a 193nm scanner lithography tool was used for the Si-fin body layout patterning under relatively high exposure energy. This achieves the ADI (after develop inspection) of 80nm from the original as-drawn Si-fin layout of 110nm. Then, a deep sub-micron plasma etcher was used for an aggressive P/R and BARC trimming down processing and both the capping TEOS and CVD-SiNx with its underlying buffer oxide layers were subsequently etched in other etching plasma chambers, respectively. Resultantly, the AMI (after mask inspection) can reach 60nm. Subsequently, both the P/R and BARC were removed with a nominal plasma ashing as well as a RCA cleaning for the final sub-micron Si-fin plasma etching. Eventually, a 60nm-width and 400nm-height bulk Si-fin body structure can be successfully etched out after a fixed time-mode silicon plasma etching.