Browsing by Author "Chen, Tung-Yang"

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On-chip detection circuit for protection design in display panel against electrical fast transient (EFT) disturbance
(2011)
Yen, Cheng-Cheng
;
Ker, Ming-Dou
;
Lin, Wan-Yen
;
Yang, Che-Ming
;
Chen, Shih-Fan
A new on-chip detection circuit is proposed for electrical fast transient (EFT) protection design in a display system. For microelectronic products, electrical transient disturbances often cause upset or frozen states under the IEC test standard. The output signal of the proposed detection circuit can be used as a firmware index to execute system automatic recovery operations and to release the EFT-induced locked states in display panels. The circuit function to detect positive or negative electrical transients has been investigated in HSPICE simulation and verified in silicon chip. The experimental results have confirmed successful circuit performance under EFT tests. With hardware/firmware co-design, the immunity of a display system against electrical transient disturbance has been significantly improved.
POWER-RAIL ESD PROTECTION CIRCUIT WITHOUT LOCK-ON FAILURE
(2009-04-02)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
Chen, Tung-Yang
An ESD protection circuit including a discharge device, a first detection circuit, and a second detection circuit. The discharge device provides a discharge path between a first power rail and a second power rail when the discharge device is activated. The discharge device stops providing the discharge path when the discharge device is de-activated. The first detection circuit is coupled between the first and the second power rails. The first detection circuit activates the discharge device when an ESD event occurs in the first power rail. The second detection circuit de-activates the discharge device when the ESD event does not occur in the first power rail.
Protection Design Against System-Level ESD Transient Disturbance on Display Panels
(2010-01-01)
Ker, Ming-Dou
;
Lin, Wan-Yen
;
Yen, Cheng-Cheng
;
Yang, Che-Ming
;
Chen, Tung-Yang
A hardware/firmware system co-design has been proposed in this work to protect display electronic products against system-level electrostatic discharge (ESD) transient disturbance. By including transient detection circuit, the firmware can execute system recovery procedure to recover all electrical functions under system-level ESD tests. The transient detection circuit is designed to detect different positive and negative fast electrical transients and verified in a 0.13 mu m CMOS process. The experimental results have confirmed that the proposed hardware/firmware design can successfully improve the susceptibility of display products against system level ESD zapping.
TRANSIENT DETECTION CIRCUIT
(2009-10-29)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
Liao, Chi-Sheng
;
Chen, Tung-Yang
A transient detection circuit coupled between a first power line and a second power line and including a first control unit, a setting unit, and a voltage regulation unit. The first control unit generates a first control signal. The first control signal is at a first level when an electrostatic discharge (ESD) event occurs. The first control signal is at a second level when the ESD event does not occur. The setting unit sets a first node. The first node is set at the second level when the first control signal is at the first level. The voltage regulation unit regulates the first node. The voltage regulation unit regulates the level of the first node at the second level when the first control signal is at the second level.
TRANSIENT DETECTION CIRCUIT FOR ESD PROTECTION
(2009-07-23)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
Liao, Chi-Sheng
;
Chen, Tung-Yang
A transient detection circuit including a detecting unit, a setting unit, and a memory unit. The transient detection circuit provides an information signal to an external instrument when an electrostatic discharge (ESD) event occurs. The detecting unit is coupled between a first power line and a second power line for detecting the ESD event. The setting unit sets a level of a first node according to the detection result. The memory unit controls the information signal according to the level of the first node. The information signal is at a first level when the ESD event occurs in the first power line.
TRANSIENT TO DIGITAL CONVERTERS
(2009-09-17)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
Liao, Chi-Sheng
;
Chen, Tung-Yang
A digital converter including a first adjustment unit and a first transient detection unit. The first adjustment unit adjusts amplitude of an electrostatic discharge (ESD) pulse to generate a first adjustment signal when an ESD event occurs in a first power line and a second power line is at a complementary level. The first transient detection unit generates a first digital code according to the first adjustment signal.
Transient-Induced Latchup in CMOS ICs Under Electrical Fast-Transient Test
(2009-06-01)
Yen, Cheng-Cheng
;
Ker, Ming-Dou
;
Chen, Tung-Yang
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The occurrence of transient-induced latchup (TLU) in CMOS integrated circuits (10) under electrical fast-transient (EFT) tests is studied. The test chip with the parasitic silicon-controlled-rectifier (SCR) structure fabricated by a 0.18-mu m CMOS process was used in EFT tests. For physical mechanism characterization, the specific "swept-back" current caused by the minority carriers stored within the parasitic PNPN structure of CMOS ICs is the major cause of TLU under EFT tests. Different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS ICs against TLU under EFT tests. By choosing the proper components in each noise filter network, the TLU immunity of CMOS ICs against EFT tests can be greatly improved.
Transient-to-Digital Converter for ESD Protection Design in Microelectronic Systems
(2008)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
Liao, Chi-Sheng
;
Chen, Tung-Yang
;
Tsai, Chih-Chung
An on-chip transient-to-digital converter for system-level electrostatic discharge (ESD) protection is proposed. The proposed transient-to-digital converter is designed to detect fast electrical transients during the system-level ESD events. The output digital thermometer codes can correspond to different ESD voltages under system-level ESD tests. The experimental results in a 0.18-mu m CMOS integrated circuit (IC) with 3.3-V devices have confirmed the detection function and digital output codes.
Transient-to-Digital Converter for Protection Design in CMOS Integrated Circuits against Electrical Fast Transient
(2009)
Yen, Cheng-Cheng
;
Ker, Ming-Dou
;
Liao, Chi-Sheng
;
Chen, Tung-Yang
;
Tsai, Chih-Chung
An on-chip transient-to-digital converter for protection design against electrical fast transient (EFT) is proposed. The proposed transient-to-digital converter is designed to detect fast electrical transients under EFT tests. The output digital codes can correspond to different EFT voltages during the EFT-induced transient disturbances. The experimental results in a 0.18-mu m CMOS integrated circuit (IC) with 3.3-V devices have confirmed the detection function and digital output codes.