Browsing by Author "Chen, W. B."

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Advanced Metal-Gate/High-kappa CMOS with Small EOT and Better High Field Mobility
(2012)
Chin, Albert
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Chen, W. B.
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Chen, P. C.
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Wu, Y. H.
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Chi, C. C.
Continuously down-scaling the operation voltage, saving energy, and maintaining high performance are the major challenge for CMOS device. Small 0.95 similar to 1.4 nm equivalent-oxide thickness (EOT) and 1.4 similar to 2.5X better mobility than universal SiO2/Si data are achieved in metal-gate/high-kappa/Ge CMOS at 1 MV/cm effective field (E-eff). These excellent performances were achieved by using interface engineering and novel process, to overcome the poor high-kappa/Ge interface reaction, low source-drain dopant activation, and n(+)/p ohmic contact. The all-Ge CMOS with measured higher electron and hole mobility has irreplaceable merits of much simpler process, lower cost, and potentially higher yield than the InGaAs-nMOS/Ge-pMOS platform for IC manufacture.
Characteristics of Cerium Oxide for Metal-Insulator-Metal Capacitors
(2010)
Cheng, C. H.
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Hsu, H. H.
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Chen, W. B.
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Chin, Albert
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Yeh, F. S.
In this article, we describe our successful fabrication of a CeO(2) metal-insulator-metal (MIM) capacitor with a low voltage nonlinearity. A low leakage current of 3.9 X 10(-7) A/cm(2) at -1 V and a small VCC-alpha similar to 421 ppm/V(2) were obtained at a high 10.8 fF/mu m(2) density for a Pt/CeO(2)/TaN MIM capacitor. The small VCC-alpha for a 15 nm thick CeO(2) dielectric (kappa similar to 20) was much better than the reported dielectrics of HfO(2), Tb-HfO(2), and Al(2)O(3)-HfO(2) at a similar kappa-value (15-20). The good analog performance was due to the combined effect of the CeO(2) dielectric and the high work-function metals. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3258042] All rights reserved.
Comparison of MONOS memory device integrity when using Hf(1-x-y)N(x)O(y) trapping layers with different N compositions
(2008-06-01)
Yang, H. J.
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Cheng, C. F.
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Chen, W. B.
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Lin, S. H.
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Yeh, F. S.
We have studied the nitrogen composition dependence of the characteristics of TaN/HfLaON/Hf(1-x-y)N(x)O(y)/ SiO(2)/Si MONOS memory devices. By increasing the N composition in the Hf(1-x-y)N(x)O(y) trapping layer, both the memory window And high-temperature retention improved. The Hf(0.3)N(0.2)O(0.5) MONOS device displayed good characteristics in terms of its +/-9-V program/erase (P/E) voltage, 100-mu s P/E speed, large initial 2.8-V memory window, and a ten-year extrapolated retention of 1.8 V at 85 degrees C or 1.5 V at 125 degrees C.
Flat band voltage control on low V(t) metal-gate/high-kappa CMOSFETs with small EOT
(2009-07-01)
Chin, Albert
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Chang, M. F.
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Lin, S. H.
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Chen, W. B.
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Lee, P. T.
The unwanted high threshold voltage (V(t)) is the major challenge for metal-gate/high-kappa CMOs especially at small equivalent-oxide-thickness (EOT). We have investigated the high V(t) issue that is due to flat-band voltage (V(fb)) roll-off at smaller EOT. A mechanism of charged oxygen vacancies formed by interface reaction was proposed to explain the V(fb) roll-off effect. This interface reaction can be decreased by inserting a thin interfacial SiON and using novel low temperature process. The self-aligned and gate-first metal-gate/high-kappa CMCSFETs using these methods have achieved low V(t) and good control of V(fb) roll-off at small 0.6-1.2 nm EOT. Crown Copyright (C) 2009 Published by Elsevier B.V. All rights reserved,
Flat band voltage control on low V-t metal-gate/high-kappa CMOSFETs with small EOT
(2009-07-01)
Chin, Albert
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Chang, M. F.
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Lin, S. H.
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Chen, W. B.
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Lee, P. T.
The unwanted high threshold voltage (V-t) is the major challenge for metal-gate/high-kappa CMOs especially at small equivalent-oxide-thickness (EOT). We have investigated the high V-t issue that is due to flat-band voltage (V-fb) roll-off at smaller EOT. A mechanism of charged oxygen vacancies formed by interface reaction was proposed to explain the V-fb roll-off effect. This interface reaction can be decreased by inserting a thin interfacial SiON and using novel low temperature process. The self-aligned and gate-first metal-gate/high-kappa CMCSFETs using these methods have achieved low V-t and good control of V-fb roll-off at small 0.6-1.2 nm EOT. Crown Copyright (C) 2009 Published by Elsevier B.V. All rights reserved,
Gate-First TaN/La(2)O(3)/SiO(2)/Ge n-MOSFETs Using Laser Annealing
(2010-11-01)
Chen, W. B.
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Wu, C. H.
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Shie, B. S.
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Chin, Albert
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電子工程學系及電子研究所
To improve device performance, laser annealing was applied to Ge n-MOSFETs, which gave a low sheet resistance of 68 Omega/sq, a small ideality factor of 1.3, and a large similar to 10(5) forward everse current in the source-drain n(+)/p junction. The laser-annealed gate-first TaN/La(2)O(3)/SiO(2)/Ge n-MOSFETs showed a high mobility of 603 cm(2)/Vs and a good mobility of 304 cm(2)/Vs at a 1.9-nm equivalent oxide thickness.
Gate-First TaN/La2O3/SiO2/Ge n-MOSFETs Using Laser Annealing
(2010-11-01)
Chen, W. B.
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Wu, C. H.
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Shie, B. S.
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Chin, Albert
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電子工程學系及電子研究所
To improve device performance, laser annealing was applied to Ge n-MOSFETs, which gave a low sheet resistance of 68 Omega/sq, a small ideality factor of 1.3, and a large similar to 10(5) forward\reverse current in the source-drain n(+)/p junction. The laser-annealed gate-first TaN/La2O3/SiO2/Ge n-MOSFETs showed a high mobility of 603 cm(2)/Vs and a good mobility of 304 cm(2)/Vs at a 1.9-nm equivalent oxide thickness.
High Performance of Ge nMOSFETs Using SiO(2) Interfacial Layer and TiLaO Gate Dielectric
(2010-01-01)
Chen, W. B.
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Chin, Albert
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Using a SiO(2) interfacial layer and a high-kappa gate TiLaO dielectric, the TaN/TiLaO/SiO(2) on Ge/Si nMOSFETs in this study showed a small 1.1-nm capacitance equivalent thickness, a good high field mobility of 201 cm(2)/(V . s) at 0.5 MV/cm, and a very low OFF-state leakage current of 3.5 x 10(-10) A/mu m. The self-aligned and gate-first metal-gate/high-kappa and Ge nMOSFETs were processed using standard ion implantation and 550 degrees C RTA. The proposed devices are fully compatible with current VLSI fabrication methods.
High Performance of Ge nMOSFETs Using SiO2 Interfacial Layer and TiLaO Gate Dielectric
(2010-01-01)
Chen, W. B.
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Chin, Albert
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Using a SiO2 interfacial layer and a high-kappa gate TiLaO dielectric, the TaN/TiLaO/SiO2 on Ge/Si nMOSFETs in this study showed a small 1.1-nm capacitance equivalent thickness, a good high field mobility of 201 cm(2)/(V . s) at 0.5 MV/cm, and a very low OFF-state leakage current of 3.5 x 10(-10) A/mu m. The self-aligned and gate-first metal-gate/high-kappa and Ge nMOSFETs were processed using standard ion implantation and 550 degrees C RTA. The proposed devices are fully compatible with current VLSI fabrication methods.
High-field mobility metal-gate/high-kappa Ge n-MOSFETs with small equivalent-oxide-thickness
(2011-01-01)
Chen, W. B.
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Cheng, C. H.
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Lin, C. W.
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Chen, P. C.
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Chin, Albert
We fabricated high performance gate-last TaN/La(2)O(3)/SiO(2) on Ge n-MOSFET. Small equivalent-oxide-thickness (EOT) of 1.9-nm and high-field mobility of 258 cm(2)/V s at 0.75 MV/cm were obtained, which were attributed to the thin SiO(2)-like barrier layer and low process temperature to prevent interfacial reaction during post-deposition annealing (PDA). (C) 2010 Elsevier Ltd. All rights reserved.
High-Performance Gate-First Epitaxial Ge n-MOSFETs on Si With LaAlO(3) Gate Dielectrics
(2010-12-01)
Chen, W. B.
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Cheng, C. H.
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Chin, Albert
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光電學院
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電子工程學系及電子研究所
This brief presents high-performance Ge n-MOSFETs with good high-field mobility of 218 cm(2)/V . s at 0.5 MV/cm, low subthreshold swing (SS) of 108 mV/dec, small equivalent oxide thickness (EOT) of 1.6 nm, low 7 x 10(-10) A/mu m OFF-state leakage, small bias temperature instability of 31 mV at 1.2 V overdrive and 85 degrees C, and full process compatibility with current very large-scale integration fabrication. These are one of the best SS and high-field mobility data among gate-first Ge n-MOSFETs using epitaxial Ge on 6-in Si wafer and proper high-kappa LaAlO(3) dielectric without using an interfacial layer. Using a different high-kappa HfAlO gate dielectric, the Ge n-MOSFETs showed poor leakage, large flatband voltage shift, and degraded EOT.
High-Performance Gate-First Epitaxial Ge n-MOSFETs on Si With LaAlO3 Gate Dielectrics
(2010-12-01)
Chen, W. B.
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Cheng, C. H.
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Chin, Albert
;
光電學院
;
電子工程學系及電子研究所
This brief presents high-performance Ge n-MOSFETs with good high-field mobility of 218 cm(2)/V . s at 0.5 MV/cm, low subthreshold swing (SS) of 108 mV/dec, small equivalent oxide thickness (EOT) of 1.6 nm, low 7 x 10(-10) A/mu m OFF-state leakage, small bias temperature instability of 31 mV at 1.2 V overdrive and 85 degrees C, and full process compatibility with current very large-scale integration fabrication. These are one of the best SS and high-field mobility data among gate-first Ge n-MOSFETs using epitaxial Ge on 6-in Si wafer and proper high-kappa LaAlO3 dielectric without using an interfacial layer. Using a different high-kappa HfAlO gate dielectric, the Ge n-MOSFETs showed poor leakage, large flatband voltage shift, and degraded EOT.
Higher Gate Capacitance Ge n-MOSFETs Using Laser Annealing
(2011-04-01)
Chen, W. B.
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Shie, B. S.
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Chin, Albert
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
By applying laser annealing (LA) on both gate dielectrics and source/drain activation, the TaN/ZrO(2)/La(2)O(3)/SiO(2) on Ge n-MOSFETs shows a high gate capacitance density, a small n(+)/p-junction ideality factor of 1.10, a small subthreshold swing (SS) of 106 mV/dec, and a good high-field mobility of 285 or 340 cm(2)/V . s after gate leakage correction at 1 MV/cm, at a small 0.95-nm equivalent oxide thickness (EOT). To the best of our knowledge, this is the first demonstration of significantly high gate capacitance in MOSFETs by LA. This is also the highest 1-MV/cm mobility at the smallest EOT of Ge n-MOSFETs and better than the SiO(2)/Si universal mobility.
Higher kappa Metal-Gate/High-kappa/Ge n-MOSFETs with < 1 nm EOT Using Laser Annealing
(2010)
Chen, W. B.
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Shie, B. S.
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Chin, Albert
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Hsu, K. C.
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Chi, C. C.
High performance metal-gate/high-kappa/Ge n-MOSFETs are reached with low 73 Omega/sq sheet resistance (R(s)), 1.10 ideality factor, 0.95 nm EOT, small 106 mV/dec sub-threshold slope (SS), good 285 cm(2)/Vs high-field (1 MV/cm) mobility and low 37 mV Delta V(t) PBTI (85 degrees C, 1 hr). This is achieved by using 30-ns laser annealing that leads to 57% higher gate capacitance, better n(+)/p junction and 10X better I(ON)/I(OFF).
Improving the retention and endurance characteristics of charge-trapping memory by using double quantum barriers
(2008-07-01)
Lin, S. H.
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Yang, H. J.
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Chen, W. B.
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Yeh, F. S.
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McAlister, Sean P.
We have studied the performance of double-quantum-barrier [TaN - Ir(3)Si] - [HfAlO - LaAlO(3)] - Hf(0.3)N(0.2)O(0.5) - [HfAlO - SiO(2)]-Si charge-trapping memory devices. These devices display good characteristics in terms of their +/- 9-V program/erase (P/E) voltage, 100-mu s P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 degrees C. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced-interface trap generation.
Interfacial layer dependence on device property of high-kappa TiLaO Ge/Si N-type metal-oxide-semiconductor capacitors at small equivalent-oxide thickness
(2009-11-23)
Chen, W. B.
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Chin, Albert
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
We have investigated the device property dependence of high dielectric-constant (high-kappa) TiLaO epitaxial-Ge/Si n-type metal-oxide-semiconductor (n-MOS) capacitors on different GeO(2) and SiO(2) interfacial layers. Large capacitance density of 3.3 mu F/cm(2), small equivalent-oxide thickness (EOT) of 0.81 nm and small C-V hysteresis of 19 mV are obtained simultaneously for MOS capacitor using ultrathin SiO(2) interfacial layer, while the device with ultrathin interfacial GeO(2) shows inferior performance of larger 1.1 nm EOT and poor C-V hysteresis of 93 mV. From cross-sectional transmission electron microscopy, secondary ion mass spectroscopy, and x-ray photoelectron spectroscopy analysis, the degraded device performance using GeO(2) interfacial layer is due to the severe Ge outdiffusion, thinned interfacial GeO(2) and thicker gate dielectric after 550 degrees C rapid-thermal anneal.
Low-Threshold-Voltage TaN/Ir/LaTiO p-MOSFETs Incorporating Low-Temperature-Formed Shallow Junctions
(2009-06-01)
Lin, S. H.
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Cheng, C. H.
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Chen, W. B.
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Yeh, F. S.
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Chin, Albert
We demonstrate a low threshold voltage (V,) of -0.17 V and good hole mobility (54 cm(2)/V (.) s at 0.8 MV/cm) in TaN/Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO(2)-covered Ni/Ga which reduced the high-kappa dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.
Low-Threshold-Voltage TaN/LaTiO n-MOSFETs With Small EOT
(2009-09-01)
Lin, S. H.
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Cheng, C. H.
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Chen, W. B.
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Yeh, F. S.
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Chin, Albert
In this letter, we report a low threshold voltage (VI) of 0.12 V in self-aligned gate-first TaN/LaTiO n-MOSFETs, at an equivalent oxide thickness of only 0.63 run. This was achieved by using Ni-induced solid-phase diffusion of SiO(2)-covered Ni/Sb that reduced the high-kappa dielectric interfacial reactions.