Browsing by Author "Chen, WF"

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Design optimization of ESD protection and latchup prevention for a serial I/O IC
(2004-02-01)
Huang, CY
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Chen, WF
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Chuan, SY
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Chiu, FC
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Tseng, JC
ESD/latchup are often two contradicting variables during IC reliability development. Trade-off between the two must be properly adjusted to realize ESD/latchup robustness of IC products. A case study on SERIAL Input/Output (I/O) IC's is reported here to reveal this ESD/latchup optimization issue. SERIAL I/O IC features a special clamping property to wake up PC's during system standby situation. Along with high voltage operation, Input/Output (I/O) protection design of this IC becomes one of the most challenging tasks in the product reliability development. In the initial development phase, ignorance of latchup susceptibility resulted in severe Electrical Overstress (EOS) damage during latchup tests, and also gave a false over estimate of ESD protection threshold through parasitic latchup paths. The latchup origin is an output PMOS and floating-well ESD triggering NMOS beside the PMOS, and the main fatal link is this high-voltage (HV) NMOS connecting to a bi-directional SCR cell. This fatal link led to totally five latchup sites and three latchup paths clarified through careful and intensive FIB failure analysis, while this powerful SCR ESD device without appropriate triggering mechanism still could not provide sufficient product-level ESD hardness. Owing to there being no design window between ESD and latchup, the original several protection schemes were all abandoned. Using this bi-directional SCR ESD cell and proper triggering PNP bipolar transistors, a new I/O protection circuit could sustain at least ESD/HBM 4 kV and latchup triggering current 150 mA tests, thus accomplish the best optimization of ESD/latchup robustness. (C) 2003 Elsevier Ltd. All rights reserved.
Low-power BIBITS encoding with register relabeling for instruction bus
(2005)
Cheng, CT
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Chiao, WH
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Shann, JJJ
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Chung, CP
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Chen, WF
Reducing power consumption of embedded system has gained much attention recently. Reducing memory bus switchings is an effective way to reduce system power since memory bus power constitutes a great portion of the system power. While many techniques exist for reducing bus power in address buses, only a few have been proposed for content-bus power reduction. We propose a Bus-Invert and Bus-Invert with transition signaling (BIBITS) encoding scheme to reduce power consumption on instruction bus. An instruction is partitioned into fields according to its format. Four elementary Boolean functions are used as encoding functions. BIBITS uses the most suitable encoding functions for different instruction partitions. We also propose a register relabeling algorithm for BIBITS encoding to further reduce bit switchings on register fields. Simulation results show that the overall average switching reduction is 64% of unencoded bus, 59% of the previous register relabeling scheme, and 33% of Petrov's bus encoding scheme. Compared with Petrov's bus encoding scheme, our scheme uses a decoding signal table only half the size to encode all basic blocks.
Low-power branch prediction
(2005)
Hu, YC
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Chiao, WH
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Shann, JJJ
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Chung, CP
;
Chen, WF
Low-power design has gained much attention recently, especially for computing on battery-powered equipments. Reducing BTB (branch target buffer) accesses is an effective way to reduce processor power consumption, since BTB consumes a significant portion of power in a processor. In this paper, we propose two approaches to reduce BTB accesses. The first approach expects the distance of every two dynamic branch instructions to be a constant n, where n can be statically profiled, and forces BTB to repose for n instructions after a BTB hit. The second approach dynamically predicts the address of the next branch instruction, and accesses BTB only on the predicted address. Multimedia/DSP benchmarks are used in our evaluation. Experimental results show that these methods can potentially reduce 22-033% of all BTB accesses.