Browsing by Author "Chen, WZ"

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1.8 V, variable gain transimpedance amplifiers with constant damping factor for burst-mode optical receiver
(2005)
Chen, WZ
;
Gan, RM
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents the design of high sensitivity and wide dynamic range transimpedance amplifiers for burst mode optical receiver. To achieve low noise and wide bandwidth design goals, both Butterworth and Bessel type TIAs are investigated, characterized, and the design techniques for noise optimization are proposed. The conversion gain of TIA is tunable with constant damping factor for wide dynamic range applications. Implemented in a 0.18 mu m CMOS technologies, the TIAs provide 66 dB Omega in the high gain mode, 57 dB Omega in the low gain mode, and are capable of operating up to 4.5 Gbps. The measured sensitivity is up to -23.3dBm with 17 dB dynamic range at BER less than 10(-12). Operating under a 1.8 V supply, the power dissipations for Butterworth and Bessel type TIA are about 37.8 mW and 43.2 mW respectively Chip size is 510 mu m x 520 mu m.
10 GHz quadrature-phase voltage controlled oscillator and prescaler
(2003)
Chen, WZ
;
Kuo, CL
;
Liu, CC
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a 10 GHz quadrature phase LC-VCO with a novel ring-array based injection-locked prescaler are presented. Fabricated in a 0.18 mum digital CMOS process, output frequency of VCO ranges from 10.03-9.35 GHz, and the prescaler performs divide-by 8 operation with locking range of 1 GHz. The measured phase noise from a 9.395 GHz carrier is -120 dBc/Hz at 5 MHz offset. Operating under a single 1.8 V supply, the VCO and prescaler respectively consume 21.6 mW and 12.6 mW only. Chip size are 1682.8 mum x 647.8 mum.
A 1.8 V, 10 Gbps fully integrated CMOS optical receiver analog front end
(2004)
Chen, WZ
;
Cheng, YL
;
Lin, DS
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A fully integrated 10 Gbps optical receiver analog front-end, includes a trans-impedance amplifier (TIA) and a limiting amplifier (LA), is fabricated using a 0.18 mum CMOS technology. The receiver front-end provides a conversion gain up to 85 dBOmega and -3 dB bandwidth of 7.6 GHz. The sensitivity of the optical receiver is - 13 dBm at a bit-error rate of 10(-12) with 2(31)-1 pseudo-random bits. 3-D symmetric transformers are utilized in the AFE design for bandwidth enhancement.
A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end
(2005-06-01)
Chen, WZ
;
Cheng, YL
;
Lin, DS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-mu m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV((pp)). In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB Omega and -3 dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12 dBm at a bit-error rate of 10(-12) with a 2(31) -1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 mu m x 1796 mu m.
A 10-Gb/s laser diode driver in 0.35 mu m BiCMOS technology
(2005)
Wang, TY
;
Chen, WZ
;
Tsai, CM
;
Huang, LR
;
Li, DU
This paper describes the design of a 10Gb/s laser diode (LD) driver in a 0.35 mu m SiGe BiCMOS technology. The LD driver delivers a biased current up to 60 mA, and a modulation current ranges from 40 mA to 100 mA. High speed operation as well as high current driving capability are achieved by means of push-pull current switching scheme. In addition, negative Miller capacitor compensation technique is adopted to enhance the signal bandwidth. The output swing of the predriver is dynamically adjustable to compromise between operating speed and overshoot. Both the modulation and biased currents are derived from a bandgap reference source. The measured rise/fall time is 47ps, and timing jitter is 22.2ps(p-p). The eye diagrams meet the specifications defined by SONET OC-192 and 10G Ethernet eye mask. Operating under 3.3V/7V supply, the total power consumption is 1.38W. Chip size is 1430 x 940 mu m(2).
A 2-V 2-GHz BJT variable frequency oscillator
(1998-09-01)
Chen, WZ
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new LC-tuned negative-resistance variable-frequency oscillator (VFO) is described. Frequency tuning is accomplished by using a variable-impedance converter (VIC) to simulate the varactor function, A negative-impedance converter provides the necessary negative resistance for oscillation and also functions as the voltage level shifters for the VIC. A low-voltage translinear circuit is used to linearize the tuning characteristic of the VFO. Implemented in a 0.8 mu m 12 GHz f(T) BiCMOS technology, the VFO has a tuning range from 1.55 to 2.02 GHz, while consuming 15 mA from a -2 V supply.
A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-mu m digital CMOS process
(2004-01-01)
Chen, WZ
;
Chang, JX
;
Hong, YJ
;
Wong, MT
;
Kuo, CL
This brief describes the design of a frequency synthesizer for 2.3/4.6-GHz wireless applications in a 0.35-mum digital CMOS process. This synthesizer provides dual-band output signals by means of frequency doubling techniques. Output frequency of the proposed synthesizer ranges from 1.87-2.3 GHz, and 3.74-4.6 GHz. This chip consumes a total power of 80 mW from a single 2-V supply, including 45 mW for dual-band output buffers. Core size is 2200 mum x 1600 mum.
A 2-V, 1.8-GHz BJT phase-locked loop
(1999-06-01)
Chen, WZ
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper describes the design of a bipolar junction transistor phase-locked loop (PLL) for Sigma Delta fractional-N frequency-synthesis applications. Implemented in a 0.8-mu m BICMOS technology, the PLL can operate up to 1.8 GHz while consuming 225 mW of power from a single -2-V supply. The entire LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A differential low-voltage current-mode logic circuit configuration is used in most of the PLL's functional blocks to minimize phase jitter and achieve low-voltage operation. The multimodulus frequency divider is designed to support multibit digital modulation. The new phase and frequency detector and loop filter contain only npn transistors and resistors and thus achieve excellent resolution in phase comparison. When phase locked to a 53.4-MHz reference clock, the measured phase noise of the 1.6-GHz output is -91 dBc/Hz at 10-kHz offset, The frequency switching time from 1.677 to 1.797 GHz is 150 mu s. Die size is 4300 x 4000 mu m(2), including the passive loop filter.
A 2.5Gbps serial-link data transceiver in a 0.35 mu m digital CMOS technology
(2004)
Chen, WZ
;
Weng, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents the design of a single chip serial link data transceiver. Incorporating with 8 to 1 multiplexer and 1 to 8 demultiplexer, the transceiving data rate ranges from 640 Mbps to 2.56 Gbps. In the transmitter side, a novel precharged type multiplexer is proposed to minimize deterministic jitter. In the receiver side, an over-sampling data recovery loop utilizing mixed-signal phase picking scheme is adopted for data resynchronization and demultiplexing. A novel phase interpolator with resistive averaging technique is proposed to generate uniformly distributed sampling phases over wide frequency range, so as to improve bit error rate performance. For data packet size less than 1000 bytes, the tolerated frequency offset between transmitter and receiver is about 1.3% by a built in elastic buffer. The measured data jitter at the transmitter side after multiplexing is 5.8 ps (rms), and is 43.3 ps (rms) at the receiver side after demultiplexing. The measured bit error rate for 2.5 Gbps data receiving is about 10(-10). Fabricated in a 0.35mum digital CMOS process, this chip occupies 2.9 mm x 2.4 mm. The total power consumption is 280 mW under 2V supply.
A 2V 2GHz BJT variable-frequency oscillator
(1997)
Chen, WZ
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An LC-tuned negative-resistance variable-frequency oscillator (VFO) is described. Frequency tuning is accomplished by using a variable impedance converter to simulate the varactor function. Implemented in a 0.8 mu m 12 GHz f(T) BiCMOS technology, the VFO has a tuning range from 1.55 GHz to 2.02 GHz, while consuming 15 mA from a -2 V supply.
A 5-GHz direct-conversion receiver with I/Q phase and gain error calibration
(2005)
Chen, WZ
;
Lee, TL
;
Lu, TY
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電機學院
;
College of Electrical and Computer Engineering
This paper describes the design of a 5GHz direct conversion receiver with phase and gain errors calibration for WLAN application. Integrated both LNA and mixer in a single chip, the conversion gain of the RF receiver is switch-able to compromise between linearity and noise performance. In addition, calibration schemes are proposed to compensate gain and phase errors in the I/Q signal paths. By means of this technique, the measured phase error is reduced to be less than 0.6 degrees and gain error less than 0.2 dB. The receiver provides a conversion gain of 28.2 dB in the high gain mode and 11.6 dB in the low gain mode within the signal bandwidth. The overall noise figure is 6.4dB in the high gain mode, and the third-order input intercept point (IIP3) is about -6.8dBm in the low gain mode. Implemented in a 0.18-mu m CMOS technology, it consumes 37.4 mW from a 1.8 V supply. Chip area is 1.64 mm(2).
A parallel multi-pattern PRBS generator and BER tester for 40(+) Gbps Serdes applications
(2004)
Chen, WZ
;
Huang, GS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents the design of a programmable PRBS generator and a BER tester according to CCITT recommendations. Implemented in a parallel feedback configuration, this IC features PRBS generation of the sequences of length 2(7)-1, 2(10)-1, 2(15)-1, 2(23)-1,and 2(31)-l b for up to 40+Gbps serdes applications with 1:16 multiplexing and demultpilexing. The mark densities of 1/2, 1/4 and 1/8 for each of the patterns are also selectable. This IC could be used as a low cost substitute for more expensive bit error rate test system. Implemented in a 0.18 mum CMOS process, the total power dissipation is 141mW.
Comparison of the recording dynamics of phenanthrenequinone-doped poly(methyl methacrplate) materials
(2001-07-01)
Mumbru, J
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Solomatine, I
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Psaltis, D
;
Lin, SH
;
Hsu, KY
A comparative analysis of phenanthrenequinone-doped poly(methyl methacrylate) materials fabricated at California Institute of Technology and National Chiao Tung University is performed in order to understand the differences exhibited in their recording and baking dynamics. (C) 2001 Published by Elsevier Science B.V.
Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-mu m digital CMOS technology
(2006-05-01)
Chen, WZ
;
Lu, CH
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電子工程學系及電子研究所
;
Innovative Packaging Research Center
;
Department of Electronics Engineering and Institute of Electronics
This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-mu m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 mu A(rms). The input sensitivity of the receiver front-end is 16 mu A for 2.5-Gbps operation with bit-error rate less than 10(-12), and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 mu m x 1500 mu m.
Exposure schedule for multiplexing holograms in photopolymer
(1999)
Lin, SAH
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Hsu, KY
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Chen, WZ
;
Whang, WT
;
光電工程學系
We present dynamics of the grating formation process in phenanthrenequinone- (PQ-) doped poly(methyl methacrylate) (PMMA) photo-polymer. The exposure schedule for multiplexing holograms to achieve equal-strength storage in a single location is described. The analysis method is valid for any saturated media, thus the results can be applied to other photo-polymer materials with similar kinetics.
Holographic data storage using photopolymer
(1999)
Hsu, KY
;
Lin, SH
;
Whang, WT
;
Chen, WZ
;
光電工程學系
We present our studies on a photopolymer of poly(methyl methacrylate) (PMMA) doped with phenathrenequinone (PQ) molecules. We describe their characteristics for holographic data storage, including photo-sensitivity, material M/#, angular selectivity, dynamic exposure schedule, absorption and scattering effect. Experimental demonstrations on multiple digital data pages stored in a polymer cube are presented.
Miniaturized 3-dimensional transformer design
(2005)
Chen, WZ
;
Hsu, KC
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
3-dimentional fully-symmetric transformers are proposed and realized in a standard CMOS technology. In contrast to their planar counterparts, the self resonant frequency (f(SR)) of the proposed architecture is improved by 26 % to 53 %, while the chip area is reduced by 40 % to 70 %. The coupling coefficient (K) can be up to 0.77 at 8 GHz in a two turn two layer architecture. Distributed capacitance model (DCM) of the 3-D transformer is also proposed f(SR) evaulation.
Phenanthrenequinone-doped poly(methyl methacrylate) photopolymer bulk for volume holographic data storage
(2000-04-01)
Lin, SH
;
Hsu, KY
;
Chen, WZ
;
Whang, WT
;
材料科學與工程學系
We present the design and fabrication of a phenanthrenequinone-doped poly(methyl methacrylate) photopolymer material. Large blocks of samples were made, and the material showed negligible shrinkage after optical exposures. We recorded and reconstructed 250 holograms at a single spot, using a 1-cm(3) block. (C) 2000 Optical Society of America OCIS codes: 210.2860, 210.4810, 160.5470.
Symmetric 3D passive components for RE ICs application
(2003)
Chen, WZ
;
Chen, WH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes novel 3-D symmetric RF passive components, including inductors, transformers, and baluns. Layout areas of these components are drastically reduced by means of stacked structure while the symmetry of input and output ports is also maintained. The area saving of 3-D inductor is up 70 %. The 1:1 transformer shows less than 0.1 % inductance mismatch in a 18 GHz range, and K is up to 0.87 at 17 GHz. The 3-D balun manifests less than 0.8 dB gain mismatch from 5.25GHz to 6GHz and phase error is about 4degrees at 5.25 GHz according to measurement results. All the components are fabricated in a 0.18 mum standard CMOS process.
Symmetric 3D passive components for RF ICs application
(2003)
Chen, WZ
;
Chen, WH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes novel 3-D symmetric RF passive components, including inductors, transformers, and baluns. Layout areas of these components are drastically reduced by means of stacked structure while the symmetry of input and output ports is also maintained. The area saving of 3-D inductor is up 70 %. The 1:1 transformer shows less than 0.1 % inductance mismatch in a 18 GHz range, and K is up to 0.87 at 17 GHz. The 3-D balun manifests less than 0.8 dB gain mismatch from 5.25GHz to 6GHz and phase error is about 4degrees at 5.25 GHz according to measurement results. All the components are fabricated in a 0.18 mum standard CMOS process.