Browsing by Author "Chen, Wan-Lu"

Now showing 1 - 2 of 2

Advanced gate-all-around fin-like poly-Si TFTs with multiple nanowire channels
(2008)
Tu, Shih-Wei
;
Liao, Ta-Chuan
;
Lin, Wei-Kai
;
Liu, Cheng-Chin
;
Tai, Ya-Hsiang
The gate-all-around (GAA) fin-like poly-Si TFTs (FinTFTs) with multiple nanowire channels (MNCs) have been fabricated using a simple process to demonstrate high performance electrical characteristics. The fin-like nanowire (NW) channel with high body thickness-to-width ratio (T-Fin/W-Fin), approximately equals to one, was realized only with a sidewall-spacer formation. The unique suspending MNCs were also achieved to build the GAA structure. By the way, the GAA-MNC Fin TFTs showed outstanding three-dimensional gate controllability and excellent electrical characteristics, which revealed a high ON/OFF current ratio (>10(8)), a low threshold voltage, a steep subthreshold swing, a near-free drain-induced barrier lowering and a good reliability. Therefore, such the high-performance GAA-MNC FinTFTs are vet-v suitable for the applications in the system-on-panel (SOP) and three-dimensional (3D) circuits.
Improving electrical performance of the scaled low-temperature poly-Si thin film transistors using vacuum encapsulation technique
(2008)
Lin, Wei-Kai
;
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Tu, Shih-Wei
;
Liu, Yen-Ting
A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with in-situ vacuum gaps has been proposed and fabricated with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH4-based passivation oxide under the vacuum process chamber. The proposed T-Gate poly-Si TFT has demonstrated to suppress the short-channel effects by simulated and measured characterization. It is attributed to the undoped offset region and vacuum gap to reduce the maximum electric field at drain Junction..