Browsing by Author "Chen, Wei-Chung"

Now showing 1 - 20 of 25

0.65V-Input-Voltage 0.6V-Output-Voltage 30ppm/degrees C Low-Dropout Regulator with Embedded Voltage Reference for Low-Power Biomedical Systems
(2014-01-01)
Chen, Wei-Chung
;
Su, Yi-Ping
;
Lee, Yu-Huei
;
Wey, Chin-Long
;
Chen, Ke-Horng
A Dynamic Bootstrap Voltage Technique for a High-Efficiency Buck Converter in a Universal Serial Bus Power Delivery Device
(2016-04-01)
Chen, Wei-Chung
;
Chou, Ying-Wei
;
Chien, Meng-Wei
;
Chen, Hsin-Chieh
;
Yang, Shang-Hsien
The dynamic bootstrap voltage (DBV) technique is proposed to keep high efficiency over wide ranges of load currents for high-power universal serial bus devices. The silicon area of the embedded power management with the DBV technique in the system-on-a-chip can be effectively reduced to 50% of the conventional design with a P-type high-side power MOSFET. Test chips fabricated in 0.25-mu m CMOS process showed a 92% peak efficiency from 1 mA to 1 A. The maximum driving current was higher than 5 A, and the efficiencywas 88%. Compared with the efficiency of the converter without the DBV technique, the efficiency of the converter with DBV technique was improved by about 28%.
A Near-Zero Cross-Regulation Single-Inductor Bipolar-Output (SIBO) Converter with an Active-Energy-Correlation Control for Driving Cholesteric-LCD
(2011)
Lee, Yu-Huei
;
Fan, Ming-Yan
;
Chen, Wei-Chung
;
Chen, Ke-Horng
;
Liu, Sheng-Fa
A near-zero cross-regulation (near-zero CR) single-inductor bipolar-output (SIBO) converter with an adaptive-energy correlation (AEC) control is proposed as a compact power management solution for driving cholesteric-LCD (Ch-LCD). The SIBO converter can provide a pair of positive and negative output voltages with only one external inductor for achieving the polarity reversion operation in Ch-LCD to obtain high-quality displays. The proposed AEC control decides energy distribution for bipolar outputs without any cross regulation through the embedded prediction function. The chip fabricated in a 0.25 mu m CMOS process demonstrates near-zero cross-regulation at bipolar outputs with 90% peak power conversion efficiency.
A Power Cloud System (PCS) for High Efficiency and Enhanced Transient Response in SoC
(2013-03-01)
Shih, Chun-Jen
;
Chu, Kuan-Yu
;
Lee, Yu-Huei
;
Chen, Wei-Chung
;
Luo, Hsin-Yu
Tradeoff between power efficiency and transient performance usually comes out during the design consideration of a power module. A configurable power supplying implementation named as the power cloud system (PCS) is proposed to handle different load conditions for simultaneously improving the power efficiency and the transient response in order to meet the system-on-chip (SoC) requirements. At heavy loads, the switching regulator takes over the energy delivery scheme in the PCS with the fast transient technique. An auxiliary power unit, which activates hybrid operation in both medium and light loads, can realize the low-dropout (LDO) regulator to provide a supplementary energy immediately in transient duration and be the high-side power switches of the switching regulator to minimize the power loss. Besides, owing to its low quiescent current of an LDO regulator, it can directly operate under the ultralight-load condition. Therefore, the satisfactory power conversion efficiency and the load transient response can be derived over a wide load range, which will certainly meet the power requirement for different operated functions in the SoC. The chip was fabricated by a 0.25-mu m CMOS process, and the experimental results show the improvements of 56% transient dip voltage and 25% transient recovery time in hybrid operation, as well as a peak efficiency of 94%.
A Pseudo Fixed Switching Frequency 2kHz/A in Optimum On-Time Control Buck Converter with Predicting Correction Technique for EMI Solution
(2014-01-01)
Chen, Wei-Chung
;
Lin, Kuei-Liang
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
;
Tsai, Tsung-Yen
This paper repots an optimum on-time (OOC) control with predicting correction technique (PCT) for ripple-based buck converter. The switching frequency (F-SW) variation is analyzed with completely considering the parasitic resistances of the components and devices. The proposed converter achieved nearly constant switching frequency over a wide load range without extra clock controlled circuits and current sensing circuits. The parameters of the parasitic resistances almost cause no influence and no restriction on F-SW performance. Actually, only the input voltage is necessary to predict the optimum on-time, and this work benefits the decease on total pin numbers. The simulation results demonstrate 0.375% Delta F-SW/F-SW and 2kHz/A Delta F-SW/Delta I-LOAD over 1.5A load current change. Consequently, pseudo constant F-SW with known noise spectrum strongly benefits the solution of electromagnetic interference (EMI) issue for system-on-chip (SoC).
A Single-Inductor Bipolar-Output Converter with 5 mV Positive Voltage Ripple for Active Matrix OLED
(2011)
Chen, Wei-Chung
;
Chiu, Chao-Chang
;
Hsieh, Chun-Yu
;
Huang, Tzu-Chi
;
Lee, Yu-Huei
This paper proposed a single inductor bipolar outputs (SIBO) switching converter for the active matrix Organic Light-Emitting Diode (AMOLED). The negative voltage is generated by the inverting buck-boost converter, which is regulated by the high signal-to-noise ratio comparator. Moreover, the boost converter is utilized to provide the positive output voltage. The proposed switching converter uses the switch sequential to reduce the positive voltage ripple to about 5 mV with the proportional-integral (PI) compensator to guarantee good line and load-regulation. Simulation results show the positive output voltage is regulated to 5V and the negative output voltage is -7V for driving the AMOLED. When the load current is 25 mA and the ESR is 30m Omega, the output voltage ripples are equal to 5 mV and 11 mV for positive and negative voltages, respectively. Besides, the load and line regulations of positive output voltage are 0.24 mV/mA and 5 mV/V, respectively. The maximum efficiency is 88.5% when the input voltage is 4.5 V and the load current is 50mA
A Single-Inductor Dual-Output Converter with Switchable Digital-or-Analog Low-Dropout Regulator for Ripple Suppression and High Efficiency Operation
(2012)
Lee, Yu-Huei
;
Chen, Wei-Chung
;
Chiu, Chao-Chang
;
Peng, Shen-Yu
;
Chu, Kuan-Yu
a single-inductor dual-output (SIDO) converter with the switchable digital-or-analog (D/A) low-dropout (LDO) regulator achieves an analog dynamic voltage scaling (ADVS) function for ripple suppression and high efficiency in system-on-achip (SoC). The ADVS function helps dynamically adjust the dropout voltage of the switchable D/A LDO regulator with analog operation for ripple suppression according to the load current. On other hand, the switchable D/A LDO regulator activates the digital operation for high efficiency at light loads since the dropout voltage of the LDO regulator can be further reduced. Besides, the bidirectional asynchronous signal pipeline (BASP) can realize the 50nA quiescent current in digital LDO regulator. This chip was fabricated by the 40 nm CMOS process. Experimental results demonstrate the switchable LDO regulator operation with the peak efficiency of 92% and the 7 mV output voltage ripple at 200 mA load because of the ripple suppression. The efficiency can be kept higher than 83% even the load current is 1 mA.
A Switchable Digital-Analog Low-Dropout Regulator for Analog Dynamic Voltage Scaling Technique
(2014-03-01)
Chen, Wei-Chung
;
Ping, Su-Yi
;
Huang, Tzu-Chi
;
Lee, Yu-Huei
;
Chen, Ke-Horng
Dual dynamic voltage scaling (DVS) techniques employed in single-inductor dual-output (SIDO) converters are used to improve the efficiency of the system-on-a-chip (SoC). One DVS technique for digital circuits is controlled by the SoC processor. This paper presents the analog DVS (ADVS) technique for analog circuits to scale voltage across the power MOSFET of the switchable digital-analog (D/A) low-dropout (LDO) regulator which is the post-regulator cascaded in series with the SIDO converter. The ADVS determines the tradeoff between voltage suppression and efficiency. Furthermore, because of the digital operation of the D/A LDO regulator, the quiescent current is further reduced at light loads while the load current requirement is minimized. In addition, the limitation of the capacitor-free LDO is significantly reduced by a few microamperes. The test chip was fabricated using a 40-nm CMOS process. Experimental results demonstrated switchable D/A LDO regulator operation with peak efficiency at 96.7% in analog operation and a 5-mV output voltage ripple at 120-mA load resulting from the advantage of ripple suppression. The power efficiency could be sustained at a value over 92.57% even when the load current decreased to 1 mu A.
A Wide Load Range and High Efficiency Switched-Capacitor DC-DC Converter With Pseudo-Clock Controlled Load-dependent Frequency
(2014-03-01)
Chen, Wei-Chung
;
Ming, Da-Long
;
Su, Yi-Ping
;
Lee, Yu-Huei
;
Chen, Ke-Horng
A high efficiency 3.3V-to-1V switched-capacitor (SC) step-down DC-DC converter with load-dependent frequency control (LFC) and deep-green mode (DGM) operation is proposed for system-on-a-chip (SoC) application. According to output loading current, the LFC technique can immediately and dynamically adjust the switching frequency through the use of pseudo-clock generator (PCG) and lead-lag detector (LLD) circuit to obtain high power conversion efficiency and small output voltage ripple over a wide loading current range. Therefore, adequate loading current supplying function and output voltage regulation can be guaranteed. Moreover, the DGM operation, similar to pulse skipping mode, can mask the switching clock to reduce power loss at ultra-light loads for further improving power efficiency. The test chip fabricated in 55 nm CMOS process demonstrates that the proposed fast transient converter can deliver wide load range from 10 mA to 250 mA with two small flying capacitors (C-F1, C-F2 = 0.1 mu F) and one output capacitor (C-OUT = 1 mu F). The peak conversion efficiency is 89% compared to the ideal value of 91% (3 * V-OUT/V-IN). In other words, the peak normalized efficiency is equal to 98%. The overall normalized efficiency is always kept higher than 90% while the output voltage ripple is guaranteed smaller than 30 mV.
Anti-ESL/ESR Variation Robust Constant-on-time Control for DC-DC Buck Converter in 28nm CMOS Technology
(2014-01-01)
Chen, Hsin-Chieh
;
Chen, Wei-Chung
;
Chou, Ying-Wei
;
Chien, Meng-Wei
;
Wey, Chin-Long
Conventional constant-on-time (COT) control for DC-DC buck converter is apt to be affected by the noise caused by parasitic effect including not properly specified and temperature dependent equivalent series resistance (ESR) and equivalent series inductance (ESL). As a result, the safety operation area (SOA) of the COT is limited by the selection of external components. In this paper, the calibrated anti-ESL (CAESL) technique and the calibrated gain and BW (CGB) technique for alleviating ESL and ESR variation, respectively, are proposed to ensure a robust COT control. Furthermore, degraded output regulation caused by enlarged ESL effect due to input battery voltage variation is also solved by the CAESL technique. The proposed COT converter fabricated in 28nm CMOS technology uses an output capacitor with an ESR smaller than 1m Omega, output ripple of 20mV, and high efficiency higher than 95%. The CAESL circuit can tolerate ESL voltage variation from 0 to 50mV even when operation temperature varies from -40 to 120 degrees C.
CCM/GM Relative Skip Energy Control and Bidirectional Dynamic Slope Compensation in a Single-Inductor Multiple-Output DC-DC Converter for Wearable Device Power Solution
(2016-08)
Su, Yi-Ping
;
Lin, Chiun-He
;
Yang, Te-Fu
;
Huang, Ru-Yu
;
Chen, Wei-Chung
Compact size wearable devices require multiple supplies with relative large loading difference, which causes serious cross regulation, large ripple, and oscillation in single-inductor multiple-output (SIMO) DC-DC converter. Thus, a continuous conduction mode/green mode (CCM/GM) relative skip energy control (RSEC) in SIMO is proposed for wearable device power solution. Different from the conventional absolute skip method, the RSEC eliminates unnecessary skip-induced voltage ripple and cross regulation with well regulation performance over wide load and voltage ranges. Optimization between efficiency and voltage ripple achieves low noise supply and reduced switching loss. In addition, smooth transition between CCM and GM provides high power and longer usage time in wearable devices. Furthermore, bidirectional dynamic slope compensation conquers subharmonic oscillation and avoids invalid pulses in the energy delivery operation of current-mode SIMO DC-DC converters. The test chip fabricated in the 0.18 mu m CMOS process occupies 2.24 mm(2) active area. Maximum output ripple, overshoot/undershoot, and cross regulation are kept below 40 mV, 27 mV, and 0.0432 mV/mA, respectively.
CCM/GM Relative Skip Energy Control in Single-inductor Multiple-output DC-DC Converter for Wearable Device Power Solution
(2014)
Su, Yi-Ping
;
Lin, Chiun-He
;
Yang, Te-Fu
;
Huang, Ru-Yu
;
Chen, Wei-Chung
Compact size wearable devices require multiple supplies with relative large loading difference, which causes serious cross regulation, large ripple and oscillation in single-inductor multiple-output (SIMO) DC-DC converter. Thus, a continuous conduction mode/green mode (CCM/GM) relative skip energy control (RSEC) in single-inductor multiple-output (SIMO) is proposed for wearable device power solution. Different from conventional absolute skip method, the RSEC eliminates unnecessary skip-induced voltage ripple and cross regulation with well regulation performance over wide load and voltage ranges. Optimization between efficiency and voltage ripple achieves low noise supply and reduced switching loss. Moreover, smooth transition between CCM and GM provides high power and longer usage time in wearable devices. The test chip fabricated in 0.18 mu m CMOS process occupies 2.24mm(2) active area. Maximum output ripple, overshoot/undershoot and cross regulation are kept below 17mV, 27mV and 0.0432mV/mA, respectively.
Differential Zero Compensator in Delay-Ripple Reshaped Constant On-Time Control for Buck Converter with Multi-layer Ceramic Capacitors
(2012)
Chen, Wei-Chung
;
Lin, Chia-Ching
;
Chen, Ke-Horng
;
電機工程學系
;
Department of Electrical and Computer Engineering
a differential-zero-compensator (DZC) technology in constant on-time control dc-dc buck converter which can be applied for the ceramic capacitors is proposed in this paper. Ceramic capacitors are widely used in industry because its low cost. However, the stability often confronts with the sub-harmonic problem related to the incorrect output capacitor and ESR used. In this paper, the proposed DZC technology remits the limitation without adding extra pins and the complexity of circuit still maintain simple. Furthermore, the proposed self-compensated on-time timer (ONT) offers the reliable on-time period with linear solution. In addition, utilizing ceramic capacitor derives smaller ripple of 8mV at 8A. High efficiency of 92.5 % can be guaranteed due to the small ESR value. Stability criteria analysis and simulation results demonstrate that the stability can be ensured even if the ESR is small than 2m Omega.
Dynamic Bootstrap Voltage Technique for High Efficiency Buck Converter in Universal Serial Bus Power Device Supplying System
(2013)
Chen, Wei-Chung
;
Chen, Ke-Horng
;
Wey, Chin-Long
;
Lin, Ying-Hsi
;
Tsai, Tsung-Yen
for high power universal serial bus (USB) devices, the dynamic bootstrap voltage (DBV) technique is proposed to keep high efficiency over a wide load range, including light and heavy loads. Besides, the silicon area of power management of the system-on-a-chip (Soc) can be effectively reduced to 50% of conventional design with P-type high-side power MOSFET. The test chip fabricated in 0.25 mu m CMOS process shows 92% peak efficiency from 1mA to 1A. The maximum driving current is higher than 3A with 88 % efficiency. Compared to that without the DBV technique, the efficiency is improved about 28%.
Label-free characterization of collagen fibers in cancerous esophagus tissues using ratiometric nonlinear optical microscopy
(1970-01-01)
Chen, Wei-Chung
;
Chen, Yu-Jen
;
Lin, Shih-Ting
;
Hung, Wei-Han
;
Chan, Ming-Che
A quantitative analytical method to discriminate among the various types of cancerous esophagus tissue is essential for accurate cancer staging. This paper reports on the use of ratiometric nonlinear optical microscopy to reveal the ratio of two-photon excited fluorescence (TPEF) to second harmonic generation (SHG) and forward to backward (F/B) SHG from single collagen fibers only in submucosa of esophageal squamous cell carcinoma. This makes it possible to accurately differentiate among the four stages of esophageal cancer, providing results that are in good agreement with histopathology. Furthermore, it is confirmed by polarization-dependent SHG that the varied SHG response in esophageal cancer tissues is mainly from the shrinkage in diameter of collagen fibers instead of the collagen triple helixes altered by cancer cells. Based on the results of TPEF/SHG and F/B SHG ratio, they can cooperatively improve the precision of diagnostics on esophageal cancer and could be transferred to other types of cancer diseases with changed collagen fibers. Impact statement The issue of classifying esophageal cancer at various developmental stages is crucial for determining the optimized treatment protocol for the patients, as well as the prognosis. Precision improvement in staging esophageal cancer keeps seeking quantitative and analytical imaging methods that could augment histopathological techniques. In this work, we used nonlinear optical microscopy for ratiometric analysis on the intrinsic signal of two-photon excited fluorescence (TPEF) and second harmonic generation (SHG) from single collagen fibers only in submucosa of esophageal squamous cell carcinoma (ESCC). The blind tests of TPEF/SHG and forward (F)/backward (B) SHG were demonstrated to compare with the histology conclusion. The discussion of sensitivity and specificity was provided via statistical comparison between the four stages of esophageal cancer. To the best of our knowledge, this is the first study of using these two ratios in combination for staging ESCC.
Linear power amplifier with a modified predistortion compensation for NCDMA applications
(2005)
Kao, Yao-Huang
;
Chen, Wei-Chung
;
傳播研究所
;
Institute of Communication Studies
The selection of the matched transistor pair in a cascaded architecture for predistortion compensation is nontrivial. In this study, a modified architecture of predistortion with two paths is presented for the high power amplifier. The goal is to develop a IOW linear power amplifier with LDMOS transistor for 8 channels NCDMA repeater from 870 to 880MHz. With the modified scheme, the improvement of intermodulation is larger than 10dB and spurious is less than 50dBc.
Pseudo AC Current Synthesizer and DC Offset-Corrected Technique in Constant-on-time Control Buck Converter for Werable Electronics
(2015)
Su, Jui-Che
;
Chen, Wei-Chung
;
Lin, Wei-Tin
;
Chou, Ying-Wei
;
Chien, Meng-Wei
Constant-on-time (COT) control with an additional current feedback in conventional buck converter has the advantage of using low equivalent series resistance (ESR) output capacitor. Unfortunately, the disadvantage is output voltage regulation accuracy is greatly deteriorated by its DC offset voltage from the current feedback. More seriously, opposite reaction between output voltage and the additional current feedback signal deteriorates transient response. In this paper, pseudo AC current synthesizer and DC voltage offset correction technique are proposed to reduce load-dependent DC offset voltage for improving load regulation. Furthermore, the transient enhancement technique instantly extends on-time and the off-time periods in load change. Test chip fabricated in UMC 28nm CMOS process demonstrated that offset voltage is improved from 65mV to 4mV. Besides, the transient response can be improved to 4 mu s and 5 mu s when load changes from 0.3 to 1.7A and vice versa, respectively. The advantages of compact size, low cost, and high performance power management can maintain wearable electronics small volume, light, and sustainable.
Pseudo-Constant Switching Frequency in On-Time Controlled Buck Converter with Predicting Correction Techniques
(2016-05-01)
Chen, Wei-Chung
;
Chen, Hsin-Chieh
;
Chien, Meng-Wei
;
Chou, Ying-Wei
;
Chen, Ke-Horng
The predicting correction technique (PCT) is proposed to achieve an adaptive on-time control for ripple-based buck converters. The switching frequency f(SW) variation is suppressed when the PCT technique considers complete parasitic resistances of the components and devices. Even without extra clock-controlled circuits and current sensing circuits, the buck converter operates with a nearly constant f(SW) over a wide load range. Parasitic resistances almost cause no influence and restriction on f(SW). Only input voltage is used to predict the adaptive on-time. Measurement results show only 0.32% in Delta f(SW) / f(SW) and 5.7 kHz/A in Delta f(SW) / Delta I-LOAD in case of 1.4 A load current change and f(SW) is 2.5 MHz. Consequently, a pseudo-constant f(SW) with well-defined noise spectrum strongly benefits the solution of electromagnetic interference (EMI) for system-on-a-chip (SoC) applications.
Pseudo-Ramp Current Balance (PRCB) Technique With Offset Cancellation Control (OCC) in Dual-Phase DC-DC Buck Converter
(2014-10-01)
Su, Yi-Ping
;
Chen, Wei-Chung
;
Huang, Yu-Ping
;
Lee, Yu-Huei
;
Chen, Ke-Horng
To cope with monolithic controller replicas and the current unbalance situation in multiphase converters, a pseudoramp current balance technique is proposed to achieve timemultiplexing current balance in voltage-mode multiphase DC-DC buck converter. With only one modulation controller, silicon area and power consumption caused by the replicas of controller can be reduced significantly. Current balance accuracy can be further enhanced since the mismatches between different controllers caused by process, voltage, and temperature variations are removed. Moreover, the offset cancellation control embedded in the current matching unit is used to eliminate intrinsic offset voltage existing at the operational transconductance amplifier for improved current balance. An explicit model, which contains both voltage and current balance loops with non-ideal effects, is derived for analyzing system stability. Experimental results show that current difference between each phase can be decreased by over 83% under both heavy and light load conditions.
Reduction of Equivalent Series Inductor Effect in Delay-Ripple Reshaped Constant On-Time Control for Buck Converter with Multi-layer Ceramic Capacitors
(2012)
Chen, Wei-Chung
;
Kang, Yu-Chi
;
Lin, Chia-Ching
;
Chen, Ke-Horng
;
Wang, Shih-Ming
The time constant, which is the product of the output capacitor and its equivalent series resistance (ESR), limits the stability of conventional constant on-time control buck converter. To meet the expected requirements, SP-CAP is mostly used as output capacitor although it deteriorates the performance of converter. On the other hand, the multi-layer ceramic capacitors (MLCC) features low cost and small equivalent series resistance (ESR) and is widely used in commercial power management ICs. However, the stability often suffers from the sub-harmonic problem due to small time constant. This paper proposes a differential-zero compensator with the noise margin enhancement (DZC-NME) technique in constant on-time control buck DC-DC converter with ceramic output capacitor. The proposed DZC-NME technique not only eliminates the limit of large time constant but also tolerates the existence of equivalent series inductor (ESL) effect. Simulation result demonstrates the function and shows smaller output ripple of 10mV and high efficiency of 91 % with ESR which smaller than 1m Omega.