Browsing by Author "Chen, Wei-Ming"

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A 13.56 MHz 40 mW CMOS High-Efficiency Inductive Link Power Supply Utilizing On-Chip Delay-Compensated Voltage Doubler Rectifier and Multiple LDOs for Implantable Medical Devices
(2014-11-01)
Wu, Chung-Yu
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Qian, Xin-Hong
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Cheng, Ming-Seng
;
Liang, Yu-An
;
Chen, Wei-Ming
In this paper, a 13.56 MHz CMOS near-field inductive link power supply (ILPS) that can deliver 20 mA output current for implantable medical devices (IMDs) is proposed and fabricated. In the proposed ILPS, the pair of inductive link coils is constructed in the spiral shape with a ferrite core to save space and increase efficiency. Experimental results have shown that the near-field coils can transmit power at the resonant frequency of 13.56 MHz with the transmission efficiency up to 76.3%. The CMOS power regulator is composed of active voltage doubler rectifier (VD) and low-dropout regulators (LDOs). In the active VD with the comparator, the input offset voltage is adjustable for delay compensation and a start-up control circuit is added to achieve robust start-up mechanism. On-chip delay compensation control with SR-latches is proposed to prevent from error glitch switching on offset voltage control and achieve accurate delay compensation so that the reverse current conduction can be avoided and the efficiency can be increased. Three fully-integrated LDOs with rectifier output voltage of 2 V to 1.8 V are realized for analog (ALDO), digital (DLDO), and reference-voltage (RLDO) circuits. Thus the performance of individual LDO can be optimized. The measured output ripple voltage of the active VD is 10.4 mV. The power conversion efficiency (PCE) is 85% under 20 mA output current. The measured dropout voltage is 384 mV. As compared with other designs, the proposed ILPS has lower ripple voltages, lower dropout voltage, and higher PCE.
A 13.56 MHZ METAMATERIAL FOR THE WIRELESS POWER TRANSMISSION ENHANCEMENT IN IMPLANTABLE BIOMEDICAL DEVICES
(2019-01-01)
Chen, Kuan-Jung
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Chen, Wei-Ming
;
Tan, Li-Yang
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Cheng, Yu-Ting
;
Ker, Ming-Dou
This paper presents a 13.56MHz metamaterial for wireless power transmission (WPT) enhancement in implantable biomedical devices based on the evanescent wave coupling mechanism. The power transmission efficiency (PTE) will increase from 46 to 51% with the metamaterial while the transmitting and receiving antennas are placed with a 1 cm distance and lcm offset horizontal misalignment, will increase from 39 to 46% with the metamaterial while the two antenna planes are placed at a distance of 1.5 cm with an axial offset of 15, and will increase from 28 to 50% with two pieces of metamaterial placed with a 0.5cm distance while the two antenna planes are placed with a 1.5 cm distance and 1 cm offset horizontal misalignment.
A 65nm CMOS Low-Power MedRadio-band Integer-N Cascaded Phase-Locked Loop for Implantable Medical Systems
(2014-01-01)
Wang, Yi-Xiao
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Chen, Wei-Ming
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Wu, Chung-Yu
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電機學院
;
College of Electrical and Computer Engineering
This paper presents a low-power MedRadio-band integer-N phase-locked Loop (PLL) system which is composed of two charge-pump PLLs cascade connected. The PLL provides the operation clock and local carrier signals for an implantable medical electronic system. In addition, to avoid the off-chip crystal oscillator, the 13.56 MHz Industrial, Scientific and Medical (ISM) band signal from the wireless power transmission system is adopted as the input reference signal for the PLL. Ring-based voltage controlled oscillators (VCOs) with current control units are adopted to reduce chip area and power dissipation. The proposed cascaded PLL system is designed and implemented in TSMC 65-nm CMOS technology. The measured jitter for 216.96 MHz signal is 12.23 ps and the phase noise is -65.9 dBc/Hz at 100 kHz frequency offset under 402.926 MHz carrier frequency. The measured power dissipations are 66 mu W in the first PLL and 195 mu W in the whole system under 1-V supply voltage. The chip area is 0.1088 mm(2) and no off-chip component is required which is suitable for the integration of the implantable medical electronic system.
A CMOS MedRadio-Band Low-Power Integer-N Cascaded Phase-Locked Loop for Implantable Medical SOCs
(2013)
Liao, Yu-Yu
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Chen, Wei-Ming
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Wu, Chung-Yu
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電機學院
;
College of Electrical and Computer Engineering
In this paper, a low power integer-N cascaded Phase-locked loop (PLL) is proposed to provide the carrier signal and clock signals for a SOC with MedRadio-band transceiver, ADC, DSP, and 13.56-MHz wireless power supply. In the proposed cascaded PLL, the first PLL provides the sampling clocks while the second PLL provides the carrier clock. Furthermore, the 13.56-MHz signal from the receiving coil of the wireless power transmission system is utilized as the input reference signal. Ring-based voltage controlled oscillator (VCO) is designed to minimize both power consumption and chip area. The proposed cascaded PLL is designed and implemented in 0.18-mu m CMOS technology. The measured phase noise is -79 dBc/Hz at 100 kHz offset under 402.9 MHz. The measured power consumptions are 0.28 mW in the first PLL and 0.46mW in the second PLL with a 1.8V supply voltage. The proposed cascaded PLL has low power dissipation, small chip area, and no off-chip components or crystal oscillator. It is suitable for the integration with implantable medical SOCs.
A CMOS Power-Efficient Low-Noise Current-Mode Front-End Amplifier for Neural Signal Recording
(2013-04-01)
Wu, Chung-Yu
;
Chen, Wei-Ming
;
Kuo, Liang-Ting
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
In this paper, a new current-mode front-end amplifier (CMFEA) for neural signal recording systems is proposed. In the proposed CMFEA, a current-mode preamplifier with an active feedback loop operated at very low frequency is designed as the first gain stage to bypass any dc offset current generated by the electrode-tissue interface and to achieve a low high-pass cutoff frequency below 0.5 Hz. No reset signal or ultra-large pseudo resistor is required. The current-mode preamplifier has low dc operation current to enhance low-noise performance and decrease power consumption. A programmable current gain stage is adopted to provide adjustable gain for adaptive signal scaling. A following current-mode filter is designed to adjust the low-pass cutoff frequency for different neural signals. The proposed CMFEA is designed and fabricated in 0.18-mu m CMOS technology and the area of the core circuit is 0.076 mm(2). The measured high-pass cutoff frequency is as low as 0.3 Hz and the low-pass cutoff frequency is adjustable from 1 kHz to 10 kHz. The measured maximum current gain is 55.9 dB. The measured input-referred current noise density is 153fA/root Hz, and the power consumption is 13 mu W at 1-V power supply. The fabricated CMFEA has been successfully applied to the animal test for recording the seizure ECoG of Long-Evan rats.
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control
(2018-11-01)
Cheng, Cheng-Hsiang
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Tsai, Ping-Yuan
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Yang, Tzu-Yi
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Cheng, Wan-Hsueh
;
Yen, Ting-Yang
A 16-channel closed-loop neuromodulation system-on-chip (SoC) for human epileptic seizure control is proposed and designed. In the proposed SoC, a 16-channel neural-signal acquisition unit (NSAU), a biosignal processor (BSP), a 16-channel high-voltage-tolerant stimulator (HVTS), and wireless power and bidirectional data telemetry are designed. In the NSAU, the input protection circuit is used to prevent MOSFET from overstressing by the high-voltage stimulations. Hence, NSAUs can share electrodes with stimulators. The auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIAs) are designed with the chopper-stabilized technique with a new offset reduction loop. The measured input-referred noise is 2.09 mu V-rms and the noise-efficiency factor (NEF) is 3.78. The entropy-and-spectrum seizure detection algorithm is implemented in the BSP with 0.76-s seizure detection latency and 97.8% detection accuracy. When the seizure onset is detected by the BSP, the HVTS with adaptive supply control delivers 0.5-3-mA biphasic current stimulation to suppress the seizure onset. The proposed SoC is powered wirelessly, and the bidirectional data telemetry is realized through the same pair of coils in 13.56 MHz. The downlink data rate is 211 Kb/s with the binary phase-shift keying (BPSK) modulation and a new BPSK demodulator. The uplink data rate is 106 Kb/s with the load-shift keying (LSK) modulation. The proposed SoC is fabricated in a 0.18-mu m CMOS technology and occupies 25 mm(2). Electrical tests have been performed to characterize the SoC performance. In vivo animal experiments using mini-pigs have been performed to successfully verify the closed-loop neuromodulation functions on epileptic seizure suppression.
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control
(2014-01-01)
Chen, Wei-Ming
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Chiueh, Herming
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Chen, Tsan-Jieh
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Ho, Chia-Lun
;
Jeng, Chi
An 8-channel closed-loop neural-prosthetic SoC is presented for real-time intracranial EEG (iEEG) acquisition, seizure detection, and electrical stimulation in order to suppress epileptic seizures. The SoC is composed of eight energy-efficient analog front-end amplifiers (AFEAs), a 10-b delta-modulated SAR ADC (DMSAR ADC), a configurable bio-signal processor (BSP), and an adaptive high-voltage-tolerant stimulator. A wire-less power-and-data transmission system is also embedded. By leveraging T-connected pseudo-resistors, the high-pass (low-pass) cutoff frequency of the AFEAs can be adjusted from 0.1 to 10 Hz (0.8 to 7 kHz). The noise-efficiency factor (NEF) of the AFEA is 1.77, and the DMSAR ADC achieves an ENOB of 9.57 bits. The BSP extracts the epileptic features from time-domain entropy and frequency spectrum for seizure detection. A constant 30-mu A stimulus current is delivered by closed-loop control. The acquired signals are transmitted with on-off keying (OOK) modulation at 4 Mbps over the MedRadio band for monitoring. A multi-LDO topology is adopted to mitigate the interferences across different power domains. The proposed SoC is fabricated in 0.18-mu m CMOS and occupies 13.47 mm(2). Verified on Long Evans rats, the proposed SoC dissipates 2.8 mW and achieves high detection accuracy 92% within 0.8 s.
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic SoC for Real-Time Epileptic Seizure Control
(2013-01-01)
Chen, Wei-Ming
;
Chiueh, Herming
;
Chen, Tsan-Jieh
;
Ho, Chia-Lun
;
Jeng, Chi
A Fully Integrated Closed-Loop Neuromodulation SoC with Wireless Power and Bidirectional Data Telemetry for Real-Time Human Epileptic Seizure Control
(2017-01-01)
Cheng, Cheng-Hsiang
;
Tsai, Ping-Yuan
;
Yang, Tzu-Yi
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Cheng, Wan-Hsueh
;
Yen, Ting-Yang
This paper presents a 16-channel closed-loop neuromodulation SoC for human seizure control. The SoC includes a 16-ch signal acquisition unit, a bio-signal processor, a 16-ch adaptive stimulator, and wireless telemetry. The signal acquisition unit achieves 3.78 NEF and shares electrodes with stimulator. The seizure detection latency is 0.76s and delivered 0.5-3mA biphasic current stimulation. The SoC is powered wirelessly and bidirectional data telemetry is realized through the same pair of coils in 13.56MHz.
A Low Power 10Bit 500kS/s Delta-Modulated SAR ADC (DMSAR ADC) for Implantable Medical Devices
(2013)
Lyu, Yuan-Fu
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Wu, Chung-Yu
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Liu, Li-Chen
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Chen, Wei-Ming
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電子工程學系及電子研究所
An architecture of SAR ADC called the delta-modulated SAR ADC (DMSAR ADC) is proposed and designed for medical device applications. In the proposed DMSAR ADC, only the voltage difference between two successive samples is resolved to reduce the conversion steps and decrease the power consumption per channel up to 66%. The experimental chip is implemented in 0.18 mu m CMOS technology. At the digital supply voltage of 1.35V and Vref=1.00V, the measured power consumption per channel is 1.38 mu W (2.71 mu W) and the measured SNDR is 56.68dB (53.89 dB) for Fin=10Hz (7kHz). The ENOB is 9.12b and FoM is 39.54fJ/step.
A Low-Power Current-Mode Front-End Acquisition System for Biopotential Signal Recording
(2012)
Chen, Wei-Ming
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Kuo, Liang-Ting
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Wu, Chung-Yu
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a new current-mode front-end amplifier for biopotential signal recording system is proposed. A current-mode preamplifier incorporates with an active feedback loop to bypass any dc current generated by tissues is designed as the first stage. A programmable gain stage and a current-mode filter are designed to adjust both gain and the low-pass cutoff frequency, respectively. The current-mode front-end amplifier is designed and fabricated in 0.18-mu m CMOS technology. The measured maximum current gain is 55.9 dB. The high-pass cutoff frequency can achieve as low as 0.3Hz and the low-pass cutoff frequency can be adjusted from 1 KHz to 10 KHz. The measured input-referred noise is 153 fA/ root Hz, and the power consumption is 13 mu W at 1-V power supply.
An 8-Channel Power-Efficient Time-Constant-Enhanced Analog Front-End Amplifier for Neural Signal Acquisition
(2015)
Chung, Jung-Chen
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Chen, Wei-Ming
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Wu, Chung-Yu
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
In this paper, an 8-channel low-power analog front-end amplifier (AFEA) with time-constant-enhanced topology is proposed for neural signal acquisition. The AFEA is composed of eight time-constant-enhanced amplifiers (TCEAs) and high-pass filters (HPFs), a multiplexed transconductor (MGM) and a transimpedance amplifier (TIA). The AFEA is designed and simulated in 65nm CMOS technology. The bandwidth of the AFEA is 7 kHz, and the maximum gain is 61.2 dB with power consumption of 1.77 mu W per channel. The TCEA is designed to reduce the high-pass cut-off frequency to 0.16 Hz and achieve a high gain of 50.7 dB with only 4 pF input capacitance. The power consumption of TCEA is 1.08 mu W under 1-V power supply. The noise efficiency factor (NEF) of the TCEA is 2.13 with 4.46 mu V-rms input-referred noise.
Design Considerations and Clinical Applications of Closed-Loop Neural Disorder Control SoCs
(2017-01-01)
Wu, Chung-Yu
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Cheng, Cheng-Hsiang
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Ou-Yang, Yi-Huan
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Chen, Chiung-Chu
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Chen, Wei-Ming
This paper presents the closed-loop neural disorder control concept and some design considerations. Two architectures of closed-loop neuromodulation for Parkinson's disease and epileptic seizure are proposed. One is a closed-loop deep brain stimulator, which meets the IEC 60601-1 standard. The other one is an implantable SoC for epileptic seizure control, which is verified by animal experiment.
Live Demonstration: The Implementation of CMOS Biopotential Signal Recording Systems
(2012)
Chen, Wei-Ming
;
Wu, Chung-Yu
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this demonstration, a CMOS biopotential signal recording system for electrocardiogram (ECG) and electroencephalogram (EEG) is presented. The system includes two individual chip modules of a multi-channel analog frond-end amplifier (AFEA) and a low-power successive approximation register analog-to-digital converter (SAR ADC). The AFEA consists of eight chopper-stabilized pre-amplifiers, an 8-to-1 analog multiplexer, and a programmable gain amplifier (PGA). The two chips are designed and fabricated by TSMC 0.18-um CMOS technology. The fabricated AFEA chip provides 40 to 74.1-dB tunable gain with 1-kHz to 7-kHz tunable low-pass cutoff frequency and 0.9-mu Vrm input referred noise. The measured SNDR of the SAR ADC is 56.68dB (53.89 dB) for Fin=10 Hz (7 kHz) with a power dissipation per channel of 2.95 mu W (5.82 mu W). The proposed system will be applied to different applications and demonstrated through internet monitoring and on-site demonstration.
The Design of 8-Channel CMOS Area-Efficient Low-Power Current-Mode Analog Front-End Amplifier for EEG Signal Recording
(2016)
Sung, Ya-Syuan
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Chen, Wei-Ming
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Wu, Chung-Yu
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電子工程學系及電子研究所
;
生醫電子轉譯研究中心
In this paper, an 8-channel area-efficient low-power current-mode analog front-end amplifier (AFEA) is designed for EEG signal recording. The AFEA is composed of eight capacitive coupled transconductors (CCGMs), current-mode band-pass filters (CMBPFs), and programmable current-gain amplifiers (PCGAs) with a multiplexer (MUX), a transimpedance amplifier (TIA), and an offset current cancellation loop (OCCL). The AFEA employs CCGM with only 2pF input capacitance to eliminate the electrode dc offset (EDO). The current-mode topology is adopted in the design of CCGMs, CMBPFs, and PCGAs to reduce the power consumption. The shared OCCL is designed to eliminate the output offset of CCGM, CMBPF and PCGA. The AFEA is designed and fabricated in 180-nm CMOS technology and the core area occupies only 1mm(2). The measured maximum gain is 82 dB. The measured input-referred noise is 3.34 mu V-rms within the bandwidth of 0.5-100 Hz. The measured maximum power consumption is 7.85 mu W per channel under power supply of 1.2V. The fabricated AFEA is applied to record the human EEG signal successfully.
The Design of CMOS General-Purpose Analog Front-End Circuit with Tunable Gain and Bandwidth for Biopotential Signal Recording Systems
(2011)
Chen, Wei-Ming
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Yang, Wen-Chia
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Tsai, Tzung-Yun
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Chiueh, Herming
;
Wu, Chung-Yu
In this paper an 8-channel CMOS general-purpose analog front-end (AFE) circuit with tunable gain and bandwidth for biopotential signal recording systems is presented. The proposed AFE consists of eight chopper stabilized pre-amplifiers, an 8-to-1 analog multiplexer, and a programmable gain amplifier. It can be used to sense and amplify different kinds of biopotential signals, such as electrocorticogram (ECoG), electrocardiogram (ECG) and electromyogram (EMG). The AFE chip is designed and fabricated in 0.18-mu m CMOS technology. The measured maximum gain of AFE is 60.8 dB. The low cutoff frequency can achieve as low as 0.8 Hz and high cutoff frequency can be adjusted from 200 Hz to 10 kHz to suit for different kinds of biopotential signals. The measured input-referred noise is 0.9 mu Vr, with the power consumption of 18 mu W per channel at 1.8-V power supply. And the noise efficiency factor (NEF) is only 1.3 for pre-amplifier.