Browsing by Author "Chen, William Po-Nien"

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A Comprehensive Investigation of Analog Performance for Uniaxial Strained PMOSFETs
(2009-02-01)
Kuo, Jack Jyun-Yan
;
Chen, William Po-Nien
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a comprehensive investigation of the analog performance for uniaxial strained PMOSFETs with sub-100 nm gate length. Through a comparison between co-processed strained and unstrained devices regarding important analog metrics such as transconductance to drain current ratio (g(m)/I(d)), dc gain, linearity, low-frequency noise, and device mismatch, the impact of process-induced uniaxial strain on the analog performance of MOS devices has been assessed and analyzed. Our results indicate that, although the drain current noise spectral density and drain current mismatch of the strained device under low gate voltage overdrive are increased because of the larger gate-bias sensitivity of carrier mobility, the strained device has almost the same low frequency and mismatch performance as the unstrained one at a given g(m)/I(d). This paper may provide insights for analog design using advanced strained devices.
Enhanced Temperature Dependence of Phonon-Scattering-Limited Mobility in Compressively Uniaxial Strained pMOSFETs
(2011-12-01)
Chen, William Po-Nien
;
Kuo, Jack Jyun-Yan
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper investigates the temperature dependence of phonon-scattering-limited mobility mu(PH) for advanced short-channel strained pMOS devices. By using the split CV method and Matthiessen's rule, surface-roughness-limited mobility mu SR and mu(PH) are successfully decoupled. This paper indicates that the temperature sensitivity of mu(PH) is proportional to T(-1.75) for a neutral stressor and becomes higher when compressive strain is applied. It is explained by the higher optical phonon energy induced by uniaxially compressive strain. Our new findings may also explain the previously reported higher temperature sensitivity of drain current present in uniaxial strained pMOSFETs.
Investigation and Analysis of Mismatching Properties for Nanoscale Strained MOSFETs
(2010-03-01)
Kuo, Jack Jyun-Yan
;
Chen, William Po-Nien
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper investigates and analyzes the matching properties of nanoscale strained MOSFETs under various bias conditions. Through a comprehensive comparison between coprocessed strained and unstrained PMOSFETs, the impact of process-induced uniaxial strain on the matching performance of MOS devices has been assessed and analyzed. Our examination indicates that, in the low-gate-voltage-overdrive (vertical bar V(gst)vertical bar) regime, the normalized drain current mismatch (sigma(Delta I(d))/I(d)) of the strained device is almost the same as that of the unstrained one at a given transconductance to drain current ratio (g(m)/I(d)). In the high vertical bar V(gst)vertical bar linear regime, the sigma(Delta I(d))/I(d) for the strained device is smaller than that of the unstrained one because of its smaller normalized current factor mismatch. In the high vertical bar V(gst)vertical bar saturation regime, the improvement in the sigma(Delta I(d))/I(d) for the strained device is further enhanced because of the reduced critical electric field at which the carrier velocity becomes saturated.
Investigation of Coulomb Mobility in Nanoscale Strained PMOSFETs
(2008-09-01)
Chen, William Po-Nien
;
Su, Pin
;
Goto, Ken-Ichi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper provides an experimental assessment of Coulomb scattering mobility for advanced strained devices. By accurate short-channel mobility extraction, we examine the impact of process-induced uniaxial strain on Coulomb mobility in short-channel pMOSFETs. Our extracted Coulomb mobility shows very weak stress dependency at room temperature. This finding has also been verified in both long- and short-channel devices by the four-point wafer bending measurement. Therefore, in order to maximize the process-induced strain efficiency on nanoscale pMOSFETs, lower surface impurity concentration is suggested to avoid the Coulomb mobility domination in carrier transport.
Series Resistance and Mobility Extraction Method in Nanoscale MOSFETs
(2009)
Chen, William Po-Nien
;
Su, Pin
;
Goto, Ken-Ichi
;
Diaz, Carlos H.
;
電子工程學系及電子研究所
This paper presents a BSIM-based method for source/drain series resistance and mobility extraction in nanoscale strained-silicon metal oxide semiconductor field effect transistors (MOSFETs) with halo implants. This method is more accurate than the conventional channel-resistance and shift and ratio method because it considers the gate-length dependence of mobility caused by local uniaxial stress and laterally nonuniform channel doping. We have verified this method using samples with different stressor/doping conditions and good agreement with experimental data has been obtained. The accuracy of the Berkeley Short-channel IGFET model (BSIM) R(sd) extraction method is also proven by simulated current-voltage characteristics with different external resistant values. Significant mobility degradation in the short-channel regime has been observed for various uniaxial stressors. This method may serve as a suitable process monitor tool for ultrashallow junction and strained process development.