Browsing by Author "Chen, Yan-Ting"

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A Fast Converging Mechanism for Load Balancing among SDN Multiple Controllers
(2018-01-01)
Chen, Yan-Ting
;
Li, Chi-Yu
;
Wang, Kuochen
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資訊工程學系
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Department of Computer Science
Load balancing among multiple controllers is a critical issue in the software-defined networking (SDN), since traffic dynamics prevent control-plane loads from being evenly distributed among controllers. Load imbalance may cause some controllers to be overloaded while the other controllers are still underutilized. Though there have been several proposed solutions, they do not consider the convergence time of load balancing. We thus propose a fast-converging load balancing (FCLB) mechanism that seeks to achieve fast convergence for balancing loads (i.e., assigning switches) among the SDN controllers. Fast convergence can rapidly release controllers from being overloaded, thereby shortly recovering network performance and preventing some unanticipated results (e.g., controller crash). Searching for the optimal solution from a large set of switch-controller combinations can lead to a large delay, which can aggravate negative impacts from overloading. We thus leverage the genetic algorithm to find a near-optimal solution. Our simulation results show that FCLB has at least 20.7% faster convergence time than the other mechanisms while achieving better load balancing performance.
A novel compound PT-262 inhibits Oct4 and Nanog on the survivin blockage and apoptosis induction in human lung cancer
(2016-04-01)
Chen, Yan-Ting
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Li, Jing-Yi
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Pan, Pei-Ying
;
Chen, Chin-Piao
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Chao, Jui-I
A novel compound PT-262 inhibits Oct4 and Nanog on the survivin blockage and apoptosis induction in human lung cancer
(2016-04-01)
Chen, Yan-Ting
;
Li, Jing-Yi
;
Pan, Pei-Ying
;
Chen, Chin-Piao
;
Chao, Jui-I
A novel synthetic compound overcomes drug resistance on EGFR (T790M) and cancer stemness in human non-small cell lung cancer
(2017-04-01)
Pan, Pei Ying
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Chang, Chien-Jen
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Liu, Kuang-Kai
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Chan, Yu-Chi
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Chen, Yan-Ting
An Efficient Application Processor Architecture for Multicore Software Video Decoding
(2015-02-01)
Tsai, Chun-Jen
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Chen, Yan-Ting
;
Tseng, Chien-Chih
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資訊工程學系
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Department of Computer Science
In this paper, we propose a new multicore application processor architecture that facilitates the adoption of the fine-granularity software-pipeline parallelism without causing an extra burden on the system bus. The proposed system-on-a-chip architecture can simultaneously support the traditional symmetric multiprocessor (SMP) and the proposed software-pipeline applications efficiently. The programming model of the proposed architecture is compatible with the existing SMP operating systems. For the implementation of the pipeline-based parallelism, new programmer-friendly system calls are suggested to take advantage of the new software-pipeline datapath. The proposed architecture with four reduced instruction set computing cores is implemented on an field-programmable gate array development board for verification. An Advanced Video Coding/H.264 baseline profile video decoder that explores the pipeline parallelism with dynamic pipeline-stage partitioning is implemented on the target platform to justify the benefits of the proposed architecture. Experimental results show that the adoption of the proposed pipeline datapath architecture into existing application processors enables new potentials in exploring software parallelism.
Dynamic Pipeline-Partitioned Video Decoding on Symmetric Stream Multiprocessors
(2015)
Wu, Ming-Ju
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Chen, Yan-Ting
;
Tsai, Chun-Jen
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資訊工程學系
;
Department of Computer Science
In this paper, we have implemented a dynamic pipeline-partitioning video decoder for the symmetric stream multiprocessor (SSMP) architecture. The SSMP architecture extends the traditional symmetric multiprocessor (SMP) architecture with dedicated per-core scratchpad memories and inter-processor communication (IPC) controllers for efficient data passing between the processor cores. The SSMP architecture allows the processor cores to cooperate efficiently in a fine-grained software pipeline fashion. A traditional software pipelined video decoder has fixed pipeline-stage partitions. The AVC/H.264 video decoder investigated in this paper dynamically assigns different stages of the video macroblock (MB) decoding tasks to different processor cores in order to maintain load balance among the processor cores. The pipeline partitioning policy is based on the queue levels of the inter-stage buffers. Experimental results show that, on average, the proposed dynamic pipeline-partitioning video decoder is 34% faster compared to a wavefront-based parallel video decoder.
Engineered spin-state transitions of two interacting electrons in semiconductor nanowire quantum dots
(2010-06-11)
Chen, Yan-Ting
;
Cheng, Shun-Jen
;
Tang, Chi-Shung
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電子物理學系
;
Department of Electrophysics
Spin properties of two interacting electrons in a quantum dot (QD) embedded in a nanowire with controlled aspect ratio and longitudinal magnetic fields are investigated by using a configuration-interaction (CI) method. The developed CI theory based on a three-dimensional parabolic model provides explicit formulations of the Coulomb matrix elements and allows for straightforward and efficient numerical implementation. Our studies reveal fruitful features of spin-singlet-triplet transitions of two electrons confined in a nanowire QD, as a consequence of the competing effects of geometry-controlled kinetic-energy quantization, Coulomb interaction, and spin-Zeeman energy. The developed theory is further employed to study various spin states of two quantum-confined electrons in the regime of "crossover" dimensionality, from quasi-two-dimensional (disklike) QDs to finite one-dimensional (rodlike) QDs.