Browsing by Author "Chen, Yi-Hang"

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Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints
(2016-07)
Chen, Yi-Hang
;
Chen, Jian-Yu
;
Huang, Juinn-Dar
;
電機學院
;
電子工程學系及電子研究所
Power dissipation has become a pressing issue of concern in the designs of most electronic system as fabrication processes enter even deeper submicron regions. More specifically, leakage power plays a dominant role in system power dissipation. An emerging circuit design style, the reconfigurable single-electron transistor (SET) array, has been proposed for continuing Moore\'s Law due to its ultra-low leakage power consumption. Recently, several works have been proposed to address the issues related to automated synthesis for the reconfigurable SET array. Nevertheless, all of those existing approaches consider mandatory fabrication constraints of SET array merely in late synthesis stages. In this article, we propose a synthesis algorithm, featuring input-variable ordering and dynamic product term ordering, for area minimization. The fabrication constraints are taken into account at every synthesis stage of proposed flow to guarantee better synthesis outcomes. We also develop a simulated annealing-based postprocess to find a proper phase assignment of each input variable for further area reduction. Experimental results show that our new methodology can achieve up to 29% area reduction as compared to existing state-of-the-art techniques.
Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints
(2014-01-01)
Chen, Yi-Hang
;
Chen, Jian-Yu
;
Huang, Juinn-Dar
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
As fabrication processes exploit even deeper submicron technology, power dissipation has become a crucial issue for most electronic circuit and system designs nowadays. In particular, leakage power is becoming a dominant source of power consumption. Recently, the reconfigurable single-electron transistor (SET) array has been proposed as an emerging circuit design style for continuing Moore\'s Law due to its ultra-low power consumption. Several automated synthesis approaches have been developed for the reconfigurable SET array in the past few years. Nevertheless, all of those existing methods consider fabrication constraints, which are mandatory, merely in late synthesis stages. In this paper, we propose a synthesis algorithm, featuring both variable reordering and product term reordering, for area minimization. In addition, our algorithm takes those mandatory fabrication constraints into account in early stages for better outcomes. Experimental results show that our new method can achieve an area reduction of up to 24% as compared to current state-of-the-art techniques.
Defect-Aware Synthesis for Reconfigurable Single-Electron Transistor Arrays
(2017-01-01)
Huang, Juinn-Dar
;
Chen, Yi-Hang
;
Lu, Jia-Shin
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
As fabrication process exploits even deeper submicron technology, power consumption is becoming one of the most critical obstacles in electronic circuit and system designs nowadays. Meanwhile, the leakage power is dominating the power consumption. Various emerging nanodevices have been developed to tackle the leakage power issue in recent years. The single-electron transistor (SET) is regarded as one of the most promising devices since several works have successfully demonstrated that it can operate with only few electrons at room temperature. Therefore, the reconfigurable SET array has been proposed to continue Moore's Law due to its ultra-low power consumption. Nevertheless, most existing synthesis algorithms assume the given SET array is defect-free. Hence, mapping a correct synthesis outcome onto a faulty SET array still yields an erroneous result. In this paper, we propose a new synthesis algorithm that guarantees the correct functionality in the presence of defects. Furthermore, the proposed technique can sometimes benefit from those defects to further reduce the mapping area. In certain cases, the required area in a faulty SET array is even smaller than that in a fault-free one. Experimental results show that our new algorithm can synthesize moderately large circuits in a reasonable runtime and achieve an area reduction of 14% as compared to the prior art.
Performance-Optimal Behavioral Synthesis with Degenerable Compound Functional Units
(2011)
Huang, Juinn-Dar
;
Chen, Yi-Hang
;
Lin, Wan-Hsien
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Since utilizing compound functional units (e. g., multiplier-accumulate) designed with shorter delay and/or smaller area than cascaded basic functional units is a well-known technique in system design, this paper presents an ILP-based approach for performance-driven behavioral synthesis with compound functional units. The algorithm maximizes the performance of a design under resource constraints by deriving all possible degenerative forms of compound functional units and by maximizing the utilization of resources. The proposed method exploits patterns acquired from available resource types to cover the target design optimally, and then guarantees that the synthesis result is with minimal latency. Experimental results show that our approach achieves significant performance improvement as compared with the prior art.
ROBDD-Based Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays
(2015)
Chen, Yi-Hang
;
Chen, Yang
;
Huang, Juinn-Dar
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The power dissipation has become a crucial issue for most electronic circuit and system designs nowadays when fabrication processes exploit even deeper submicron technology. In particular, leakage power is becoming a dominant source of power consumption. In recent years, the reconfigurable singleelectron transistor (SET) array has been proposed as an emerging circuit design style for continuing Moore\'s Law due to its ultra-low power consumption. Several automated synthesis techniques for area minimization have been developed for the reconfigurable SET array in the past few years. Nevertheless, most of those existing methods focus on variable and product term reordering during SET mapping. In fact, minimizing the number of product terms can greatly reduce the area as well, which has not been well addressed before. In this paper, we propose a dynamic shifting based variable ordering algorithm that can minimize the number of disjoint sum-of-product terms extracted from the given ROBDD. Experimental results show that the proposed method can achieve an area reduction of up to 49% as compared to current state-of-the-art techniques.
Throughput Optimization for Latency-Insensitive System with Minimal Queue Insertion
(2011)
Huang, Juinn-Dar
;
Chen, Yi-Hang
;
Ho, Ya-Chien
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
As fabrication process exploits even deeper submicron technology, global interconnect delay is becoming one of the most critical performance obstacles in system-on-chip (SoC) designs nowadays. Recent years latency-insensitive system (LIS), which enables multicycle communication to tolerate variant interconnect delay without substantially modifying pre-designed IP cores, has been proposed to conquer this issue. However, imbalanced interconnect latency and communication back-pressure residing in an LIS still degrade system throughput. In this paper, we present a throughput optimization technique with minimal queue insertion. We first model a given LIS as a quantitative graph (QG), which can be further compacted using the proposed techniques, so that much bigger problems can be handled. On top of QG, the optimal solution with minimal queue size can be achieved through integer linear programming based on the proposed constraint formulation in an acceptable runtime. The experimental results show that our approach can deal with moderately large systems in a reasonable runtime and save about 28% of queues compared to the prior art.
Two-Staged Parallel Layer-Aware Partitioning for 3D Designs
(2014-01-01)
Chen, Yi-Hang
;
Chen, Yi-Ting
;
Huang, Juinn-Dar
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
As compared to two-dimensional (2D) ICs, 3D integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a promising solution for vertical connection, it also occupies significant silicon estate and incurs reliability problem. Because of these challenges, minimizing the number of TSVs becomes an important design issue. Therefore, in this paper, we propose a parallel layer-aware partitioning algorithm, featuring both divergence stage and convergence stage, for TSV minimization in 3D structures. In the divergence stage, we employ OpenMP for the parallelization of 2-way min-cut partitioning and get the initial solution, and then refine it in the convergence stage. Experimental results show that the proposed two-staged algorithm can reduce the number of TSVs by up to 39% as compared to several existing methods.