Browsing by Author "Chen, Yi-Kuang"

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A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System
(2009)
Lee, Yu-Huei
;
Wang, Shih-Jung
;
Yang, Yao-Yi
;
Zheng, Kuo-Lin
;
Chen, Po-Fung
The proposed power management module with 1 V low-voltage PWM controller and dynamic self-biasing mechanism is designed to integrate with ultra-wide band (UWB) system. The on-chip pre-regulator with power conditioning circuit provides a constant and noiseless supply voltage. Instead of using large external compensation circuit, the compensation enhancement multistage amplifier increases system loop gain and stabilizes the system. Moreover, the proposed self-biasing mechanism enhances the power conversion efficiency by 4 % through the handover technique. The fabricated power management module occupies 0.356 mm(2) silicon in 65nm CMOS. With the excellent line/load transient response and the highest efficiency about 93.5%, the proposed power management has the qualification to be integrated in today's system-on-chip (SoC) applications.
A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System
(2010-11-01)
Lee, Yu-Huei
;
Yang, Yao-Yi
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
;
Wang, Shih-Jung
The proposed power management module with a typical 1.2 V low-voltage PWM (LV-PWM) controller and dynamic voltage scaling (DVS) function is designed using 65 nm technology for integration with the ultra-wide band (UWB) system. The on-chip pre-regulator with a power conditioning circuit can provide a regulated supply voltage to the LV-controller. Moreover, the proposed handover technique can achieve the self-biasing mechanism to further reduce power dissipation. To operate in low voltage, the proposed compensation enhancement multistage amplifier (CEMA) can achieve high loop gain and ensure system stability without using any external compensation component. The fabricated power management module occupies 0.356 mm(2) silicon area with an excellent line/load transient response. Owing to the DVS function, the proposed power management can meet the power requirement in the UWB system and other RF transceiver systems.
A High Efficiency and Compact Size 65nm Power Management Module with 1.2V Low-Voltage PWM Controller for UWB System Application
(2009)
Lee, Yu-Huei
;
Wang, Shih-Jung
;
Yang, Yao-Yi
;
Zheng, Kuo-Lin
;
Chen, Po-Fung
This 65 nm power management module with 1.2 V low-voltage PWM controller aims to integrate with ultra-wideband (UWB) system to get high efficiency and compact size. The on-chip pre-regulator with power conditioning circuit provides a constant and noiseless supply voltage. Thus, the voltage variation of battery has less effect on the low-voltage PWM controller. The proposed compensation enhancement multistage amplifier (CEMA) increases system loop gain and stabilizes the system without off-chip compensation circuit. With excellent line/load transient response, the proposed power management has the highest efficiency about 92% and 0.995 mm(2) silicon die area.
An Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters with 91% Peak Efficiency
(2010)
Lee, Yu-Huei
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
;
Yang, Yao-Yi
;
Wang, Shih-Jung
This interleaving energy-conservation mode control for single-inductor dual-output converter uses the superposition technique to yield the optimal average inductor current and 91% peak efficiency. Neither a freewheel stage nor a post-regulator is needed at nominal conditions. The output voltage ripple appears notably minimized over 50% by means of current interleaving at full load. The chip occupies 1.44 mm(2) in 65 nm CMOS and integrates with a 3D architecture for ultra-wide band system.
Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters With 91% Peak Efficiency
(2011-04-01)
Lee, Yu-Huei
;
Yang, Yao-Yi
;
Wang, Shih-Jung
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
The proposed single-inductor dual-output (SIDO) converter with interleaving energy-conservation mode (IECM) control is designed using 65 nm technology to power the ultra-wide band (UWB) system. The energy-conservation mode (ECM) control generates four different energy delivery paths for dual buck outputs with only one inductor. In addition, the superposition technique is used to achieve a minimized inductor current level. The average inductor current is equal to the summation of two output loads. Moreover, the IECM control activates the interleaving operation through the current interleaving mechanism to provide large driving capability as well as to reduce the output voltage ripple. As a result, 91% peak efficiency is derived and the output voltage ripple appears notably minimized by 50% using current interleaving at heavy load. The test chip occupies 1.44 mm(2) in 65 nm CMOS and integrates with a three-dimensional (3-D) architecture for inductor integration.