Browsing by Author "Chen, Yu-Hua"

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A study on airlines' differentiated cargo service strategies
(2013-01-01)
Hsu, Chaug-Ing
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Chen, Yu-Hua
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Chen, Wei-Ting
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運輸與物流管理系註：原交通所+運管所
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Department of Transportation and Logistics Management
This study analyzes how an airline operates differentiated cargo services to meet shipping demand for different goods so as to enhance its service level, air freight demand, and total profit. The shipping alternative choice model assumes shippers with different demand characteristics choose the alternative with the lowest transportation and inventory costs between express and standard shipping services offered by different airlines. The study then formulates airline cost functions with respect to providing standard and express services. Furthermore, the study explores demand-supply interactions and constructs a mathematical programming model to determine flight frequencies and shipping charges for standard and express services by maximizing the object airline's total profit. The results show that those shipping high-value freights tend to select express shipping services and, for the object airline, operating differentiated cargo services rather than the current standard services can raise its market share and total profit by 19.4% and 8.6%, respectively. Moreover, for perishable goods stored in lower temperature-control devices, the charges should be higher. The results also show that not only airlines, but also shippers, can markedly reduce their costs and enhance their competitive advantages with express shipping services. (C) 2012 Elsevier Ltd. All rights reserved.
A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application
(2012-06-01)
Ko, Cheng-Ta
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Hsiao, Zhi-Cheng
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Chang, Yao-Jen
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Chen, Peng-Shu
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Hwang, Yu-Jiau
Thin wafer/chip stacking with vertical interconnect by a Cu through-silicon via (TSV) and a Cu/Sn microjoint is one of the candidates for 3-D integration. The insertion loss of the two-chip stack was evaluated with different TSV pitches, microbump diameters, and chip thicknesses to realize the signal transmission effects in high-speed digital signaling via TSV and microjoint interconnection. In addition, a wafer-level 3-D integration scheme with Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding was demonstrated. Key technologies, including TSV interconnection, microbumping, hybrid bonding, wafer thinning, and backside RDL formation, were well developed and integrated to realize 3-D integration. This paper presents a complete study of the structure design, the process condition, and the electrical and reliability assessment of the wafer-level 3-D integration scheme. This 3-D integration scheme with excellent electrical performance and reliability provides a promising solution for 3-D memory application.
An RDL-First Fan-Out Panel-Level Package for Heterogeneous Integration Applications
(2019-01-01)
Lin, Yu-Min
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Wu, Sheng-Tsai
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Wang, Chun-Min
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Lee, Chia-Hsin
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Huang, Shin-Yi
Technologies of Fan-outpanel-level packaging (FOPLP) are studies in this paper. First, the warpage control of a molded panel is a crucial problem for FOWLP technology development. In this paper, finite element analysis (FEA) is applied to study the influence of back end of the line (BEOL) process-induced warpage, as well as characterization for simulation, and investigation of each single process. In our process, a liquid release material is coated onto a 370 mm x 470 mm glass carrier. After baking, three layers of redistribution layer (RDL), passivation, and Cu leads are fabricated on the panel with coating, exposing, developing, lithography, and electroplating processes. Silicon test chips with a size of 16 mm x 10 mm and micro solder bumps with a pitch of 90 mu m are thinned down to 150 mu m. Test chips are then flip-chip bonded onto glass carrier with pre-bond and reflow proces. After panel molding, a laser debonding method, another key technology advancement, is utilized for panel debond. Debond performance, which is directly related to laser parameter and panel-level package (PLP) structure, is critical. After debonding, the molded panel is cleaned, followed by dicing and OSP coating processes, and then the electrical performance of the interconnection is evaluated. Reliability tests at the component level, such as pre-condition, thermal cycling test (TCT), and unbiased HAST (uHAST), are performed. The demonstration of RDL-first PLP technology without interposers proves its great potential in heterogeneous integration applications.
Breakthrough in Cu to Cu Pillar-Concave Bonding on Silicon Substrate with Polymer Layer for Advanced Packaging, 3D, and Heterogeneous Integration
(2017-01-01)
Yang, Yu-Tao
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Yu, Ting-Yang
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Kuo, Shu-Chiao
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Huang, Tai-Yuan
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Yang, Kai-Ming
In this paper, finite element method (FEM) simulations are carried out with pillar-concave structure using silicon substrate, silicon substrate with polyimide (PI) and with polybenzoxazole (PBO) for realization of Cu-Cu bonding at low temperature. Parameters of bonding temperature, pillar diameter, concave sidewall angle, and multilayer of concave structure are all considered in simulation. In addition, pillarconcave bonding is successfully demonstrated on silicon substrates with bonding temperatures ranging from 60 degrees C to 100 degrees C. Simulation and fabrication results of concept show potential impacts on current semiconductor packaging method with advantages such as high adhesive strength of polymer on various types of substrates, simplified manufacturing process, solder free interconnect and packaging process, Cu-Cu direct bonding at temperature lower than 100 degrees C, and high tolerance in surface roughness.
Investigation of Pillar-Concave Structure for Low-Temperature Cu-Cu Direct Bonding in 3-D/2.5-D Heterogeneous Integration
(2020-08-01)
Chou, Tzu-Chieh
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Yang, Kai-Ming
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Li, Jian-Chen
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Yu, Ting-Yang
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Yang, Yu-Tao
With the advantage of high surface-roughness tolerance, the pillar-concave Cu-Cu direct bonding without chemical-mechanical planarization (CMP) is investigated in detail, including the mechanism of thermal compensation, analysis of roughness, bonding strength, and bonding reliability. With the special design of Cu bond structure, excellent bonding results can be achieved under low thermal budget (150 degrees C for 1 min, atmosphere) with even high roughness of bonding surface. In addition, the pillar-concave scheme applied to fan-out panel-level package (FOPLP) has been demonstrated, showing the high feasibility of this scheme to realize applications in heterogeneous integration.
Low Temperature Cu-Cu Gang Bonding for RDL-First Fan-Out Panel Level Package
(2019-01-01)
Yang, Kai-Ming
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Chou, Tzu-Chieh
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Ko, Cheng-Ta
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Lin, Chen-Hao
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Chen, Yu-Hua
In this paper, low temperature (190-220 degrees C) Cu-Cu gang bonding at a low vacuum pressure is demonstrated. The low temperature technologies can be applied to the RDL-first Fan-Out panel level package (FOPLP).
Low-Temperature Cu-Cu Direct Bonding Using Pillar-Concave Structure in Advanced 3-D Heterogeneous Integration
(2017-09-01)
Yang, Yu-Tao
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Chou, Tzu-Chieh
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Yu, Ting-Yang
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Chang, Yu-Wei
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Huang, Tai-Yuan
Low-temperature Cu-Cu bonding utilizing pillar and concave on silicon substrate with and without polymer layer is successfully implemented at 200 degrees C under atmospheric pressure. Finite-element method (FEM) simulations on stress and deformation generated during bonding process are also presented in order to discuss their influence on bonding result of several pillar diameters and of concave sidewall angles originating from the manufacturing process. The alteration of parameters in FEM simulations would also be investigated to enhance the bonding outcome. The parameters include the diameter of pillar, the sidewall angle of concave, the shape of the concave opening, the addition of extra polymer layer under Cu concave layer, the bonding temperature, and the pitch of the pillar-concave structure. The implementation of Cu-Cu bonding using pillar-concave structure could have a prospective effect on existing packaging methods in semiconductor industry with benefits of applicability to various sorts of substrates and low bonding temperature.
Non-Planarization Cu-Cu Direct Bonding and Gang Bonding with Low Temperature and Short Duration in Ambient Atmosphere
(2019-01-01)
Chou, Tzu-Chieh
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Yang, Kai-Ming
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Li, Jian-Chen
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Yu, Ting-Yang
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Chung, Ying-Ting
Low temperature (150 degrees C) and short duration Cu-Cu direct bonding, without planarization, and gang bonding approaches are demonstrated with excellent bond strength, electrical characteristics, and reliability. The concept is based on the high stress-led inducing deformation and internal friction to achieve low temperature bonding. In addition, the bonding structure has the advantage of high roughness tolerance on surface without CMP requirement. Compared to current products using Cu-Cu direct bonding at 350-400 degrees C with long duration and vacuum requirement, the breakthrough of proposed schemes provides the feasibility for product realization in 3D integration packaging.
Optimization of laser release process for throughput enhancement of fan-out wafer-level packaging
(2018-01-01)
Lee, Chia-Hsin
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Su, Jay
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Liu, Xiao
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Wu, Qi
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Lin, Jim-Wein
Fan-out wafer-level-packaging (FOWLP) technology has been developed with various advantages, such as smaller form factor, lower cost, and simplified supply chain for heterogeneous integration. There have been several process schemes like chip-first or chip-last FOWLP integration discussed widely in conferences in recent years. One process in all of these process schemes has in common is the use of a temporary carrier for subsequent redistribution layer (RDL) formation, chip stacking and molding processes. Although the separation of a temporary carrier from the reconstituted wafer could be achieved without significant hurdles, there were few studies addressing optimization of carrier separation for throughput enhancement. Thus, this paper is designed to address the needs in optimizing carrier separation process based upon laser ablation technology. Two phases of experiments were designed to select the appropriate laser release layer and define optimal laser settings. The first experiment was used to evaluate correlation of the laser absorption, laser energy, and spot pitch versus completeness of laser ablation. The second experiment included RDL-first FOWLP integration. At first, 300-mm glass carriers (1000 mu m thick) with coefficient of thermal expansion of 8 ppm/degrees C were treated by selected laser release layers. After deposition of 0.05-mu m Ti/0.15 mu m Cu on the glass carrier, passivation of around 8 mu m was coated and patterned by lithography for electroplating Cu interconnections with a density of approximately 10% of the surface area. Subsequently, die bonding, build-up layers, or molding compound were applied on top to form a 200-mu m reconstituted wafer. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 355-nm laser to determine optimal throughput. Experiments to study correlation of laser release layer with laser settings along with a demonstration of full RDL-first FOWLP integration are discussed thoroughly to address the need of throughput enhancement, which could serve as cornerstone for realizing cost-effective RDL-first FOWLP.
Simulation Analysis of Structure Design for Low Temperature Cu-Cu Direct Bonding in Heterogeneous Integration and Advanced Packaging Systems
(2018-01-01)
Pan, Yu-Ming
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Yang, Yu-Tao
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Chou, Tzu-Chieh
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Yu, Ting-Yang
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Yang, Kai-Ming
In order to realize Cu-Cu bonding at low temperature, Cu pillar-concave structures on silicon substrate and on silicon substrate with another polymer layer, polyimide (PI), are both investigated through simulation. Height of Cu pillar, thickness of upper and lower silicon substrate, and thickness of Cu concave are simulated in this paper. The proposed structure could have great impacts on current semiconductor packaging technology, such as improvement of joint strength, enhancement of adhesive strength between various substrates, a Cu-Cu bonding process lower than 200 degrees C with simplified manufacturing process.
Study on Low Temperature Cu Bonding and Temporary Bond/De-Bond for RDL-First Fan-Out Panel Level Package
(2017-01-01)
Ko, Cheng-Ta
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Yang, Kai-Ming
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Lin, Jim-Wein
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Wang, Chih-Lun
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Chou, Tzu-Chieh
In this study, Cu-Cu bonding with pillar-concave structure on a polymer layer was investigated to realize better bonding quality at lower temperature, while a low-stress release layer for temporary bond and de-bond by laser ablation was demonstrated to handle a glass panel for re-distribution layer (RDL) process. The low temperature technology can be potentially applied for RDL-first fan-out panel level package (FOPLP).