Browsing by Author "Chen, Yung-Chen"

Now showing 1 - 2 of 2

Fabrication and RTN Characteristics of Gate-All-Around Poly-Si Junctionless Nanowire Transistors
(2016)
Yang, Chen-Chen
;
Chen, Yung-Chen
;
Lin, Horng-Chih
;
Chang, Ruey-Dar
;
Li, Pei-Wen
Short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors were fabricated using the control available through cost-effective I-Line lithographic patterning and spacer techniques. This scheme enables the production of GAA JL poly-Si NW transistors with channel length of as short as 120 nm and effective width of 49 nm, featuring significant improvement in subthreshold swing (SS) and transconductance (Gm). The shrunken channel allows us to monitor clear random telegraph noise (RTN) signals under a sufficiently large gate overdrive condition.
Study on Random Telegraph Noise of Gate-All-Around Poly-Si Junctionless Nanowire Transistors
(2017-01-01)
Yang, Chen-Chen
;
Peng, Kang-Ping
;
Chen, Yung-Chen
;
Lin, Horng-Chih
;
Li, Pei-Wen
In this work we study the random telegraph noise (RTN) characteristics of short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors. The test devices were fabricated with I-line-based lithography in combination with novel spacer-etching techniques for aggressively shrinking the channel dimension. Based on the tiny nanowire channel and short-channel length, we are able to detect clear RTN signals as the gate voltage is sufficiently large. Location of the trap responsible for the RTN is estimated to be 1.13 nm within the gate oxide away from the oxide/channel interface.