Browsing by Author "Chen, Zuow-Zun"

Now showing 1 - 6 of 6

A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology
(2016-12-01)
Zhao, Yan
;
Chen, Zuow-Zun
;
Du, Yuan
;
Li, Yilei
;
Al Hadi, Richard
This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53-0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7-2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than -74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power.
A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology
(2016-12)
Zhao, Yan
;
Chen, Zuow-Zun
;
Du, Yuan
;
Li, Yilei
;
Al Hadi, Richard
This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53-0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7-2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than -74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power.
A 16Gb/s 14.7mW Tri-Band Cognitive Serial Link Transmitter with Forwarded Clock to Enable PAM-16 / 256-QAM and Channel Response Detection in 28 nm CMOS
(2016)
Du, Yuan
;
Cho, Wei-Han
;
Li, Yilei
;
Wong, Chien-Heng
;
Du, Jieqiong
A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm(2) in 28nm CMOS. It achieves a maximum data rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 mu W/Gb/s/dB considering channel condition.
An Integrated 0.56THz Frequency Synthesizer with 21GHz Locking Range and-74dBc/Hz Phase Noise at 1MHz Offset in 65nm CMOS
(2016)
Zhao, Yan
;
Chen, Zuow-Zun
;
Virbila, Gabriel
;
Xu, Yinuo
;
Al Hadi, Richard
Digital PLL for Phase Noise Cancellation in Ring Oscillator-Based I/Q Receivers
(2016)
Chen, Zuow-Zun
;
Li, Yilei
;
Kuan, Yen-Cheng
;
Hu, Boyu
;
Wong, Chien-Heng
A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator phase noise, including supply-induced phase noise, is extracted from digital phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in digital domain. The receiver prototype fabricated in 65nm CMOS technology achieves phase noise reduction from - 88 to - 109dBc/Hz at 1MHz offset, and an integrated phase noise (IPN) reduction from - 16.8 to - 34.6dBc, when operating at 2.4GHz.
DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers
(2017-04-01)
Chen, Zuow-Zun
;
Kuan, Yen-Cheng
;
Li, Yilei
;
Hu, Boyu
;
Wong, Chien-Heng
In this paper, a low overhead phase noise cancellation technique for ring oscillator (RO)-based quadrature receivers is presented. The proposed technique operates in background and extracts RO phase noise as well as supply-induced phase noise from the digital phase-locked loop. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain. A receiver prototype is fabricated in standard 65-nm CMOS technology. It demonstrates a phase noise reduction from -88 to -109 dBc/Hz at 1-MHz offset and an integrated phase noise reduction from -16.8 to -34.6 dBc when operating at 2.4 GHz.