Browsing by Author "Chen Kuan-Neng"

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Bonding method for three-dimensional integrated circuit and three-dimensional integrated circuit thereof
(2013-08-13)
Chen Kuan-Neng
;
Hsu Sheng-Yao
The present invention discloses a bonding method for a three-dimensional integrated circuit and the three-dimensional integrated circuit thereof. The bonding method comprises the steps of: providing a substrate; depositing a film layer on the substrate; providing a light source to light onto the film layer to form a graphic structure; forming a metal co-deposition layer by a first metal and a second metal that are co-deposited on the film layer; providing a first integrated circuit having the substrate, the film layer and the metal co-deposition layer sequentially; providing a second integrated circuit that having the metal co-deposition layer, the film layer and the substrate sequentially; and the first integrated circuit is bonded with the second integrated circuit at a predetermined temperature to form a three-dimensional integrated circuit.
ELECTRICAL TEST STRUCTURE APPLYING 3D-ICS BONDING TECHNOLOGY FOR STACKING ERROR MEASUREMENT
(2013-03-14)
Chen Kuan-Neng
;
Li Shih-Wei
A 3D integrated circuit including a first wafer and a second wafer is provided. The first wafer includes a first conduction pattern. The second wafer includes a second conduction pattern which is electrically connected to the first conduction pattern. A displacement between the first wafer and the second wafer is determined by a resistance of the first conduction pattern and the second conduction pattern.
Electrical test structure applying 3D-ICS bonding technology for stacking error measurement
(2013-10-01)
Chen Kuan-Neng
;
Li Shih-Wei
A 3D integrated circuit including a first wafer and a second wafer is provided. The first wafer includes a first conduction pattern. The second wafer includes a second conduction pattern which is electrically connected to the first conduction pattern. A displacement between the first wafer and the second wafer is determined by a resistance of the first conduction pattern and the second conduction pattern.
ESD PROTECTION STRUCTURE FOR 3D IC
(2012-06-21)
Chen Kuan-Neng
;
Lai Ming-Fang
;
Chen Hung-Ming
An electrostatic discharge (ESD) protection structure for a 3D IC is provided. The ESD protection structure includes a first active layer, a through-silicon via (TSV) device and a second active layer. The TSV is disposed in the first active layer, and the second active layer is stacked with the first active layer. The second active layer includes a substrate and an ESD protection device, wherein the ESD protection device having a doping area embedded in the substrate, and the ESD protection device electrically connects the TSV device.
Heterostructure containing IC and LED and method for fabricating the same
(2014-03-25)
Chen Kuan-Neng
;
Ko Cheng-Ta
;
Lo Wei-Chung
A heterostructure containing IC and LED and a method of fabricating. An IC and an LED are established with the IC having a first electric-conduction block and a first connection block. The IC electrically connects to the first electric-conduction block. A first face of the LED has a second electric-conduction block and a second connection block. The LED is electrically connected to the second electric-conduction block. The first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block, and the first electric-conduction block are electrically connected with the second electric-conduction block to form a heterostructure. The heterostructure provides functions of heat radiation and electric communication for IC and LED.
Heterostructure containing IC and LED and method for fabricating the same
(2013-09-17)
Chen Kuan-Neng
;
Ko Cheng-Ta
;
Lo Wei-Chung
A heterostructure contains an IC and an LED. An IC and an LED are initially provided. The IC has at least one first electric-conduction block and at least one first connection block. The IC electrically connects with the first electric-conduction block. The first face of the LED has at least one second electric-conduction block and at least one second connection block. The LED electrically connects to the second electric-conduction block. Subsequently, the first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block. The first electric-conduction block is electrically connected with the second electric-conduction block and forms a heterostructure. The system simultaneously provides functions of heat radiation and electric communication for the IC and LED resulting in a high-density, multifunctional heterostructure.
Integrated circuit device
(2014-02-18)
Chen Kuan-Neng
;
Lai Ming-Fang
;
Chen Hung-Ming
An integrated circuit device includes: a first chip including a first substrate and a main circuit formed on said first chip; a second chip stacked on the first substrate and including a second substrate that is independent from the first substrate, and a protective circuit for protecting the main circuit; and a conductive channel unit extending from the protective circuit and electrically connected to the main circuit.
Integrated Circuit Device
(2013-07-04)
Chen Kuan-Neng
;
Lai Ming-Fang
;
Chen Hung-Ming
An integrated circuit device includes: a first chip including a first substrate and a main circuit formed on said first chip; a second chip stacked on the first substrate and including a second substrate that is independent from the first substrate, and a protective circuit for protecting the main circuit; and a conductive channel unit extending from the protective circuit and electrically connected to the main circuit.
INTERCONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE
(2015-02-05)
Chen Kuan-Neng
;
Chang Yao-Jen
An interconnection structure of a semiconductor device is provided, where the interconnection structure is constructed in a semiconductor substrate. The interconnection structure includes a first through silicon via and a second through silicon via both penetrating the semiconductor substrate, and the first through silicon via is spaced from the second through silicon via by a distance ranged from 2 μm to 40 μm.
Submicron connection layer and method for using the same to connect wafers
(2015-02-10)
Chen Kuan-Neng
;
Chang Yao-Jen
A submicron connection layer and a method for using the same to connect wafers is disclosed. The connection layer comprises a bottom metal layer formed on a connection surface of a wafer, an intermediary diffusion-buffer metal layer formed on the bottom metal layer, and a top metal layer formed on the intermediary diffusion-buffer metal layer. The melting point of the intermediary diffusion-buffer metal layer is higher bottom metal layers may form a eutectic phase. During bonding wafers, two top metal layers are joined in a liquid state; next the intermediary diffusion-buffer metal layers are distributed uniformly in the molten top metal layers; then the top and bottom metal layers diffuse to each other to form a low-resistivity eutectic intermetallic compound until the top metal layers are completely exhausted by the bottom metal layers.
THREE-DIMENSIONAL COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE
(2012-09-13)
Chen Kuan-Neng
;
Chang Yao-Jen
A three-dimensional complementary metal oxide semiconductor device comprises a bottom wafer having a first-type strained MOS transistor; a top wafer stacked on the bottom wafer face to face or face to back, having a second-type strained MOS transistor arranged opposite to the first-type strained MOS transistor, and having a plurality of metal pads and a plurality of TSVs connected to the metal pads; and a hybrid bonding layer arranged between the bottom wafer and the top wafer, having metallic-bonding areas connecting the first-type and second-type MOS transistors to TSVs and a non-metallic bonding area filled in all space except the metallic bonding areas, so as to bond the bottom and top wafers.
THREE-DIMENSIONAL INTEGRATED CIRCUIT
(2014-06-26)
Tan An-Nan
;
Chen Hung-Ming
;
Chen Kuan-Neng
A three-dimensional integrated circuit, including a first adhesive bonding layer, a first chip, a second chip, and an inter-stratum thermal pad, is provided. The first adhesive bonding layer has a first surface and a second surface opposite to each other. The first chip is disposed on the first surface of the first adhesive bonding layer. The first chip includes a hot zone. The second chip is disposed on the second surface of the first adhesive bonding layer. The inter-stratum thermal pad is embedded in the first adhesive bonding layer and faces to the hot zone.