Browsing by Author "Cheng, An-Che"

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A Formal Method to Improve SystemVerilog Functional Coverage
(2012-01-01)
Cheng, An-Che
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Yen, Chia-Chih
;
Jou, Jing-Yang
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Improving functional coverage efficiently in a verification environment based on constrained random simulation could be a difficult task, since some design states are hard to be reached by random input patterns. On the other hand, manually crafting direct test patterns may be time consuming. In this paper, a functional test pattern generation (FTPG) framework is proposed to automatically produce deterministic test patterns for complete coverage. The framework is based on the functional coverage model (covergroup) provided by SystemVerilog, and it could be easily integrated to modern digital design flow. We synthesize a practical subset of covergroup language constructs to enable FTPG by a SAT-solver. An algorithm called MRRS is proposed to minimize the potential large complexity of the synthesized circuits. Preliminary experimental results demonstrate that MRRS could facilitate FTPG to achieve 43X speed-up in average while the maximum speed-up can reach 67X. To the best of our knowledge, this is the first paper which proposes an FTPG method that utilizes covergroups.
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog
(2014-11-01)
Cheng, An-Che
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Yen, Chia-Chih (Jack)
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Val, Celina G.
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Bayless, Sam
;
Hu, Alan J.
SystemVerilog provides powerful language constructs for verification, and one of them is the covergroup functional coverage model. This model is designed as a complement to assertion verification, that is, it has the advantage of defining cross-coverage over multiple coverage points. In this article, a coverage-driven verification (CDV) approach is formulated as a simultaneous Boolean satisfiability (SAT) problem that is based on covergroups. The coverage bins defined by the functional model are converted into Conjunction Normal Form (CNF) and then solved together by our proposed simultaneous SAT algorithm PLNSAT to generate stimuli for improving coverage. The basic PLNSAT algorithm is then extended in our second proposed algorithm GPLNSAT, which exploits additional information gleaned from the structure of SystemVerilog covergroups. Compared to generating stimuli separately, the simultaneous SAT approaches can share learned knowledge across each coverage target, thus reducing the overall solving time drastically. Experimental results on a UART circuit and the largest ITC benchmark circuits show that the proposed algorithms can achieve 10.8x speedup on average and outperform state-of-the-art techniques in most of the benchmarks.
Resource-Aware Functional ECO Patch Generation
(2016)
Cheng, An-Che
;
Jiang, Iris Hui-Ru
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Jou, Jing-Yang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Functional Engineering Change Order (ECO) is necessary for logic rectification at late design stages. Existing works mainly focus on identifying a minimal logic difference between the original netlist and the revised netlist, which is called a patch. The patch is then implemented by technology mapping using spare cells. However, there may be insufficient spare cells around the physical location of the patch, or the wires connecting spare cells are too long, thus causing timing violations and routing congestion. In this paper, we propose a resource-aware functional patch generation approach by gate count and wiring cost estimations. In particular, we estimate the number of spare cells required by a patch and define a cost of wire length on it, which considers the physical location of the patch and a set of nearby spare cells. As a result, the patch with minimal wiring cost instead of minimal size is produced. The experiments are conducted on nine industrial testcases. These testcases reflect real problems faced by designers, and the results show our method is promising.