Browsing by Author "Cheng, C. F."

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A program-erasable high-k Hf0.3N0.2O0.5 MIS capacitor with good retention
(2007-10-01)
Yang, H. J.
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Chin, Albert
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Chen, W. J.
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Cheng, C. F.
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Huang, W. L.
We describe a programmable-erasable MIS capacitor with a single high-kappa Hf0.3N0.2O0.5 dielectric layer. This device showed a capacitance density of similar to 6.6 fF/mu m(2), low program and erase voltages of +5 and -5 V, respectively, and a large Delta V-fb memory window of 1.5 V. In addition, the 25 degrees C data retention was good, as indicated by program and erase decay rates of only 2 and 6.2 mV/dec, respectively. Such device retention is attributed to the deep trapping level of 1.05 eV in the Hf0.3N0.2O0.5.
Comparison of MONOS memory device integrity when using Hf(1-x-y)N(x)O(y) trapping layers with different N compositions
(2008-06-01)
Yang, H. J.
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Cheng, C. F.
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Chen, W. B.
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Lin, S. H.
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Yeh, F. S.
We have studied the nitrogen composition dependence of the characteristics of TaN/HfLaON/Hf(1-x-y)N(x)O(y)/ SiO(2)/Si MONOS memory devices. By increasing the N composition in the Hf(1-x-y)N(x)O(y) trapping layer, both the memory window And high-temperature retention improved. The Hf(0.3)N(0.2)O(0.5) MONOS device displayed good characteristics in terms of its +/-9-V program/erase (P/E) voltage, 100-mu s P/E speed, large initial 2.8-V memory window, and a ten-year extrapolated retention of 1.8 V at 85 degrees C or 1.5 V at 125 degrees C.
HtLaON n-MOSFETs using a low work function HfSix gate
(2007-12-01)
Cheng, C. F.
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Wu, C. H.
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Su, N. C.
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Wang, S. J.
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McAlister, S. P.
At a 1.2-nm equivalent oxide thickness, HfSix/Hf0.7La0.3ON n-MOSFETs showed an effective work function of 4.33 eV, a low threshold voltage of 0.18 V, and a peak electron mobility of 215 cm(2)/(V center dot s). These self-aligned and gate-first HfSix/Hf0.7La0.3ON n-MOSFETs were processed using standard ion implantation and 1000-degrees C rapid thermal annealing, making them fully compatible with current very large scale integration fabrication lines.
PD-SOI MOSFET Body-to-Body Leakage Scaling Trend and Optimization
(2008)
Lo, H. C.
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Luo, W. C.
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Lu, W. Y.
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Cheng, C. F.
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Wu, Benny
Body-to-Body leakage (BBL) in stacked transistor configuration has been characterized by different back gate biases (Vbg), SOI thicknesses, and poly spacings. BBL increases significantly from 65nm to 45nm node mainly due to smaller poly spacing and shallower S/D junctions. By implant optimization and reduction of the SOI thickness, BBL can be reduced below reverse junction leakage level.
The Characteristics and Control of Body-to-Body Leakage Current in PD-SOI
(2009)
Lo, H. C.
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Luo, W. C.
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Lu, W. Y.
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Cheng, C. F.
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Chen, T. L.
Body-to-body leakage (BBL) current in a partially depleted silicon-on-insulator (PD-SOI) device is increased significantly as polyspacing (PS) is reduced in technology scaling. We found out that the BBL has a great impact to Vt variation. We have demonstrated that the BBL can be minimized drastically by implant optimization. The dependence of the BBL on silicon film thickness, e-SiGe structure, and dopant diffusivity is also discussed in this paper. The layout effect of the BBL current in PD-SOI devices has been characterized with different PSs, device widths, and polylengths. Finally, we have demonstrated that the BBL current can be reduced below junction leakage level. (C) 2009 The Electrochemical Society. [DOI:10.1149/1.3223971] All rights reserved.
Very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions
(2007)
Cheng, C. F.
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Wu, C. H.
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Su, N. C.
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Wang, S. J.
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McAlister, S. P.
We report very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good phi(m-eff) of 5.3 and 4.1 eV, low V(t) of +0. 05 and 0.03 V, high mobility of 90 and 243 cm(2)/Vs, and small 85 degrees C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.