Browsing by Author "Cheng, Chao-Chung"

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A 1280x720 pixels 30Frames/s H.264/MPEG-4 AVC intra encoder
(2006)
Cheng, Chao-Chung
;
Ku, Chun-Wei
;
Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an HDTV size H.264/MPEG-4 AVC intra encoder suitable for DSC and digital video camera applications. The chip reduces the gate count by saving the costly plane mode and enhances the video quality with the improved cost function. With careful scheduling and high performance function unit, the developed chip can easily support 29.46M pixels/s still image encoding and real-time moving picture intra coding of HDTV 720p@30fps video application when clocked at 117.28MHz under 0.18um CMOS process.
A 61 MHz 72K gates 1280x720 30FPS H.264 intra encoder
(2007)
Li, De-Wei
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Ku, Chun-Wei
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Cheng, Chao-Chung
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Lin, Yu-Kun
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Chang, Tian-Sheuan
This paper presents an HD720p 30 frames per see H.264 intra encoder operated at 61MHz with just 72K gate count. We achieve the low cost and low operating frequency with the highly utilized variable pixel scheduling, and a modified three-step fast algorithm. Thus, the resulted design only needs half of operating frequency and reduces 30% of area cost compared to the previous HD720p intra encoder design.
A bandwidth efficient subsampling-based block matching architecture for motion estimation
(2005)
Chin, Hao-Yun
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Cheng, Chao-Chung
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Lin, Yu-Kun
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
We have developed a new pel subsampling-based search hardware for motion estimation called quartet-pel motion estimation (QME). The memory access of search range memory can be reduced to 25%. The computational complexity can also be reduced to 25% with respect to full-search block matching algorithm (FBMA). On the other hand, flexible and efficient hardware architecture is also implemented. The flexibility is based on the configuration of processing unit, and adjustable candidate number. In addition, complete veimundon and testing methods are also considered.
A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC video coding
(2007-05-01)
Wang, Yu-Jen
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Cheng, Chao-Chung
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Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a fast algorithm and its VLSI architecture for H.264 fractional motion estimation. Motivated by the high correlation of cost between neighboring fractional pel position, the proposed algorithm efficiently explores the neighborhood position around the minimum one and thus skips other unlikely ones. Thus, the proposed search pattern and early termination under constant quantization parameter can reduce about 50% of computation complexity compared to that in reference software but only with 0.1-0.2 dB peak signal-to-noise ratio degradation and less than 2% of bit rate increase. The VLSI architecture of the proposed algorithm thus can save 40% of area cost due to only half of the processing elements and save 14% of searching time when compared with the previous design.
A fast fractional pel motion estimation algorithm for H.264/MPEG-4 AVC
(2006)
Wang, Yu-Jen
;
Cheng, Chao-Chung
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a fast algorithm for H.264 fractional ME. Motivated by the highly correlation of cost between neighboring fractional pel position, the proposed algorithm efficiently explores the neighborhood position around the minimum one and thus skips other unlikely ones. Thus, the proposed algorithm can complete the search by only examining 8 or 9 search points instead of 17 search points in the search algorithm of reference software. Early termination technique is applied in every single search point The simulation result shows that the proposed algorithm can reduce about 50% of computation complexity compared to that in reference software but only with 0.1-0.2 dB PSNR degradation and less than 2% of bit rate increase.
A high-definition H.264/AVC intra-frame codec IP for digital video and still camera applications
(2006-08-01)
Ku, Chun-Wei
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Cheng, Chao-Chung
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Yu, Guo-Shiuan
;
Tsai, Min-Chi
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Chang, Tian-Sheuan
This paper presents a real-time high-definition 720p@30fps H.264/MPEG-4 AVC intra-frame codec IP suitable for digital video and digital still camera applications. The whole design is optimized in both the algorithm and architecture levels. In the algorithm level, we propose to remove the area-costly plane mode, and enhance the cost function to reduce hardware cost and to increase the processing speed while provide nearly the same quality. In the architecture design, in additional to the fast module implementation the process is arranged in the macroblock-level pipelining style together with three careful scheduling techniques to avoid the idle cycles and improve the data throughput. The whole codec design only needs 103 K gate count for a core size of 1.28 x 1.28 mm(2) and achieves real-time encoding and decoding at 117 and 25.5 MHz, respectively, when implemented by 0.18-mu m CMOS technology.
An in-place architecture for the deblocking filter in H.264/AVC
(2006-07-01)
Cheng, Chao-Chung
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Chang, Tian-Sheuan
;
Lee, Kun-Bin
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This brief presents an in-place computing design for the deblocking filter used in H.264/AVC video coding standard. The proposed in-placed computing flow reuses intermediate data as soon as data is available. Thus, the intermediate data storage is reduced to only the four 4 x 4 blocks instead of whole 16 x 16 macroblock. The resulting design can achieve 100 MHz with only 13.41K gate count and support real-time deblocking operation of 2K x IK@30 Hz video application when clocked at 73.73 MHz by using 0.25-mu m CMOS technology.