Browsing by Author "Cheng, Chia-Hsiang"

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A Flash Scheduling Strategy for Current Capping in Multi-Power-Mode SSDs
(2017-01-01)
Chang, Li-Ping
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Cheng, Chia-Hsiang
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Lin, Kai-Hsiang
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資訊工程學系
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Department of Computer Science
Solid state disks (SSDs) employ internal parallelism for high throughput, but concurrent flash operations can draw a high instantaneous current. Due to power budgeting or power-source changing, SSDs could be forced into a new operation mode with a lower current supply limit. This study presents a flash scheduling algorithm to optimize the SSD internal parallelism subject to the current limit. Based on realistic flash current models, our scheduler decides the actual starting times of every flash operation, and it efficiently examines the peak current only at a few time points. Our experiments show that our approach outperformed existing methods, and its feasibility had been verified on the OpenSSD platform.
Current-Aware Flash Scheduling for Current Capping in Solid State Disks
(2020-02-01)
Chang, Li-Pin
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Cheng, Chia-Hsiang
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Chang, Shu-Ting
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Chou, Po-Han
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資訊工程學系
Solid state disks (SSDs) employ internal parallelism to boost their input/output (I/O) performance, but a high degree of flash parallelism inevitably consumes a high level of current. To budget power or support multiple power sources, system software may force an SSD into a new power mode that has a specific current supply limit. This paper introduces a firmware approach to optimize SSD internal parallelism subject to a current supply limit. The proposed method involves two steps. First, we constructed current models of flash operations on the basis of real-world measurement results. Second, we designed a firmware scheduler to determine the actual starting time of each flash operation. The proposed scheduler accounted for flash aging, process variation, and internal resource contention, and it avoided any current cap violation by checking a few time points instead of every unit of time. Our experimental results indicated that the proposed approach outperformed existing methods with respect to I/O response time and throughput under realistic workloads.
Development and characterization of the thermal behavior of packaged cascode GaN HEMTs
(2016-01-01)
Chou, Hsin-Ping
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Cheng, Stone
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Cheng, Chia-Hsiang
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Chuang, Chia-Wei
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機械工程學系
This study investigates the heat generation behavior of packaged normally-on multi-finger AlGaN/GaN high electron mobility transistors (HEMTs) that are cascoded with a low-voltage MOSFET (LVMOS) and a SiC Schottky barrier diode (SBD). By foremost carrying out electro-thermal simulation and related thermal measurements with infrared thermography and Raman spectroscopy for basic 5 mm GaN HEMTs, the location of hot spot in operating device can be obtained. Based on the outcome, further packaged cascode GaN HEMT is analyzed. A hybrid integration of the GaN-HEMT, LVMOS, and SiC SBD are assembled on a directly bonded copper (DBC) substrate in the four-pin metal case TO-257 package. The metal plate is used as both the source terminal and heat sink. The analytical results of thermal investigation are confirmed by comparing them with the infrared thermographic measurements and numerical results obtained from a simulation using Ansys Icepak. For a power dissipation of less than 11.8 W, the peak temperature of the GaN HEMTs is 118.7 degrees C, obtained from thermal measurements. (C) 2015 Elsevier Ltd. All rights reserved.