Browsing by Author "Cheng, Ching-Hwa"

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A Low-Cost Scalable Voltage-Frequency Adjustor for Implementing Low-Power Systems
(2013)
Cheng, Ching-Hwa
;
Hsu, Sheng-Wei
;
Guo, Jiun-In
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The proposed low-cost, scalable, synthesizable Voltage-Frequency Adjustor (VFA) design provides voltage and frequency automatic adjustments for implementing low-power systems. This design is effective in reducing power consumption from managing the supplied current and clock frequency for the structurally dynamic varying systems. The VFA supplied electrical current amount and voltage level are automatically adjusted from sensing the voltage drop of the fanout load. This adjustment mechanism controls the activated power switch quantity to allow a structure varied design that can obtain a stable fanin voltage level, regardless of the designed module that is dynamically added or removed from the system. Compared to the conventional dynamic voltage frequency scaling technique, the VFA is cost effective and can be easily integrated with the target design as a single chip. The experimental results show that the combination of VFA chips and an H. 264 video decoder is successfully validated with 49%similar to 68% power reduction compared to the case that the H.264 video decoder directly uses an outer power supply.
A Power-Aware Quad-Voltage H.264 Encoder Chip for Wireless Panoramic Endoscope Applications
(2015)
Xiao, An-Tia
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Yang, Shiang-Ren
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Miao, Yuan-Hsiang
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Cheng, Ching-Hwa
;
Guo, Jiun-In
Voltage scaling is an efficient way to reduce dynamic power consumption for digital circuits. In this paper, a hierarchical multiple voltage ( HMulti-Vdd) technology is proposed to design a power-aware H.264 intra-frame encoder for wireless panoramic endoscope applications. The proposed design adopts quad supply voltages to reduce power consumption without performance degradation. A progressive voltage difference technique is adopted in the proposed design for preventing from the penalty from using level shifters on performance and power consumption. The quad-voltage test chip has been successfully validated and has shown a 40% average reduction of power consumption, as compared to the same design using a single supply voltage.
A Robust Data Retention Characteristic of Sol-Gel-Derived Nanocrystal Memory by Hot-Hole Trapping
(2010-07-01)
Wu, Chi-Chang
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Ko, Fu-Hsiang
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Yang, Wen-Luh
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You, Hsin-Chiang
;
Liu, Fu-Ken
A new sol-gel-derived Ti(x)Zr(y)Si(z)O nanocrystal (NC) memory with a high-performance data retention characteristic is demonstrated by the hot-hole-trapping method. Prior to rapid thermal annealing, the high-density NC layer is formed by depositing a well-mixed solution of titanium tetrachloride, silicon tetrachloride, and zirconium tetrachloride. The electrical properties of the sol-gel-derived NC memory are demonstrated in terms of memory window, charge retention, program speed, and endurance. The memory window of the NC memory from the novel hot-hole-trapping mechanism can be achieved up to 4.18 +/- 0.21 V, and long retention times obtained from extrapolation up to 10(6) s are observed as 8%, 13%, and 21% window narrowing under respective temperatures of 25 degrees C, 85 degrees C, and 125 degrees C. The good electrical performance is attributed to the contribution of the high density of isolated NCs and hole-trapped into the deep-trap energy level, so no significant lateral and vertical charge leakage occurs.
A Variable-Voltage Low-Power Technique for Digital Circuit System
(2016)
Xiao, An-Tai
;
Miao, Yung-Siang
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Cheng, Ching-Hwa
;
Guo, Jiun-In
;
電子工程學系及電子研究所
A swing variable voltage technique (CK-Vdd) is proposed to reduce power consume for generic digital circuit system. The proposed CK-Vdd generates a swing variable voltage, which is different from the conventional constant voltage (Vdd) to the digital circuit. The swing voltage is produced from using Voltage Frequency Adjustor (VFA) and Frequency Duty-Cycle Adjustor (FDCA) circuits. The clock rising and falling signals fanin FDCA to generate an adjustable high-low signal to control VFA generates high-low cycling swing voltage. When the clock is at positive-level, a generic positive-edge digital circuit will need large operation current. CK-Vdd supply high-voltage to the digital circuit at this time. On the other hand, when the clock signal transfers to the low-level, CK-Vdd can supply low-voltage to reduce power consumption. From reducing the supply current to the digital circuit at low-level clock, the digital circuit power consumption can be reduced. We implement the CK-Vdd technique in a H. 264 video decoder test chip based on TSMC 90 nm CMOS process. The result shows that when CK-Vdd voltage is 0.7v similar to 0.9v it can save average 32% power consumption. To the maximum, decoder chip can save as high as 45% power consumption.
ISCAS2015 Live Demonstration A Wireless Panoramic Endoscope System Design and Implementation for Minimally Invasive Surgery
(2015-01-01)
Cheng, Ching-Hwa
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Hung, Sheng-Ping
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Guo, Jiun-In
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Liu, Kai-Che
;
Wu, Chi-Hsiang
Minimally Invasive Surgery (MIS) is a current major surgery technique. A chief problem with MIS is its narrow field of vision. A wireless MIS Panoramic Endoscope (WMISPE) is developed and implemented to provide doctors with broad fields of view. A WMISPE features a combination of video overlapping and video stitching. The panoramic video apparatus has two side-by-side endoscopic lenses that provide wide-angle inputs for video stitching. A WMISPE can provide doctors with panoramic videos, so that they can easily discriminate an organ's position between surgical operations. Experimental results show that WMISPE can enhance the video size to 158%. A low-power multi-mode video decoder (MMVD) is used to validate the stitching videos. The whole system is validated by personal computer, an embedded system, and an H.264 decoder chip. The test chip is successfully validated after system integration, and obtains about a 24% reduction in power consumption, which is better than that of the same design using a single supply voltage. The animal vivo experimental videos have been successfully validated.
Reduction of current mismatching in the switches-in-source CMOS charge pump
(2013-12-01)
Shiau, Miin-Shyue
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Hsu, Heng-Shou
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Cheng, Ching-Hwa
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Weng, Hsiu-Hua
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Wu, Hong-Chong
In this paper, the charge pump (CP) based on a switches-in-source architecture is to be improved by gain-boosting amplifiers for phase-locked loops (PLLs). In our design, two differential amplifiers were employed in this CP to reduce the effect of the channel length modulation in MOS transistors. As a result, the up and down currents will be rather independent of the output voltage transformed by the capacitive low pass filter (LPF). This circuit was implemented using TSMC 0.18-mu m CMOS technology and was investigated at a power supply of 1.8 V. The measured mismatch was less than 1% for the output voltage ranging from 0.4 to 1.4 V. This result is lower than that of the dynamic current-matching CP with feedback tuning on the same architecture. A comparison will be presented and discussed. (C) 2013 Elsevier Ltd. All rights reserved.
SONOS memories with embedded silicon nanocrystals in nitride
(2008-07-01)
Liu, Mei-Chun
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Chiang, Tsung-Yu
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Kuo, Po-Yi
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Chou, Ming-Hong
;
Wu, Yi-Hong
We have successfully demonstrated SONOS memories with embedded Si-NCs in silicon nitride. This new structure exhibits excellent characteristics in terms of larger memory windows and longer retention time compared to control devices. Using the same thickness 2.5 nm of the bottom tunneling oxide, we found that N(2)O is better than O(2) oxide. Retention property is improved when the thickness of N(2)O is increased to 3.0 nm.