Browsing by Author "Cheng, H. C."

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A novel technique to fabricate 28 nm p-MOSFETs possessing gate oxide integrity on an embedded SiGe channel without silicon surface passivation
(2012-12-12)
Yu, M. H.
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Liao, M. H.
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Huang, T. C.
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Wang, L. T.
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Lee, T. L.
A novel technique to create a suspending stacked gate oxide and subsequently to fill in an embedded SiGe channel (ESC) between the gate oxide and the underlying silicon substrate is proposed for the first time to fabricate 28 nm p-metal-oxide-semiconductor field-effect transistors (p-MOSFET). Without Si surface passivation on the ESC, such an ESC structure could achieve a p-FET transconductance (G(m)) gain of 26% higher and a better I-on-I-off performance gain of 8% than that of conventional strained Si p-FETs with the source/drain (S/D) SiGe. Better S/D resistance (R-sd) in the resistance versus gate length plot and improved swing slope of the I-d-V-gs plot indicates higher mobility in the ESC devices. Moreover, the off-state gate current of the ESC structure is also comparable to the conventional ones. From the x-ray photoelectron spectrum analysis, only the Si-O bonding, and no Ge-O bonding at the SiGe/SiO2 interface could account for this superior gate oxide integrity for the ESC and strained Si structure. Therefore, such a novel technique with an ESC structure is very promising for the 28 nm p-MOSFET devices era.
Characteristics of Zinc Oxide Thin Film Transistors Fabricated by Location-Controlled Hydrothermal Method
(2010)
Yang, P. Y.
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Wang, J. L.
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Tsai, W. C.
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Wang, S. J.
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Chen, P. C.
In this paper, high-performance Zinc oxide (ZnO) thin-film transistors (TFTs) with bottom-gate (BG) structure and artificially location-controlled lateral grain growth have been prepared by low-temperature hydrothermal method. As the proper design of source/drain structure of ZnO/Ti/Pt thin films, the lateral grain growth can be artificially controlled in the desired location and the vertical grain boundary perpendicular to the current flow in the channel region can be reduced to single one. As compared with the conventional sputtered ZnO BG-TFTs, the proposed location-controlled hydrothermal ZnO BG-TFTs (W/L = 250 mu m/10 mu m) demonstrated the higher field-effect mobility of 6.09 cm(2)/V.s, lower threshold voltage of 3.67 V, larger on/off current ratio above 10(6), and superior current drivability, which can be attributed to the high-quality ZnO thin films with the reduced vertical grain boundaries in the channel region.
Co-delivery of paclitaxel and cetuximab by nanodiamond enhances mitotic catastrophe and tumor inhibition.
(2015)
Chao, J. I.
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Liao, W. S.
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Lin, Y. W.
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Lin, J.
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Cheng, H. C.
Co-delivery of paclitaxel and cetuximab by nanodiamond enhances mitotic catastrophe and tumor inhibition.
(2015)
Chao, J. I.
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Liao, W. S.
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Lin, Y. W.
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Lin, J.
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Cheng, H. C.
Controlled density growth of carbon nanotubes and its improvement on field emission properties
(2004)
Juan, C. P.
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Tsai, C. C.
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Chen, K. J.
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Hong, W. K.
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Lin, K. C.
The density distribution of the CNTs is one of the crucial parameters for the field emission property of CNTs.We use an inactive thin film layer that was deposited on the catalyst to effectively control the density of the CNTs. The results showed the improved field emission property could be obtained with a thin SiO layer on the catalyst layer as the precursor. For the 3.5 nm Fe and 3.5 nm SiO on 3.5 nm Fe as the catalyst, the turn-on field can be reduced from 3.7 V/ mu m. to 2.2 V/ mu m and the field emission current density increased from 2.6x 10(-8) A/cm(2) to 2.4x 10(-4) A/cm(2) when the applied field was 4 V/mu m. The extremely low turn-on field of 1.3 V/ mu m was also discovered for the CNTs grown with the precursor contained 1.5 nm SiO on 1.5 nm Fe; the extremely high emission current density of 4x 10(-2) A/cm(2) was also achieved under the low electric field of 3.5 V/ mu m.
Excimer laser crystallization of a-Si1-xGex thin films and its applications to the low-temperature poly-Si1-xGex TFTs
(2004)
Chang, T. K.
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Chen, B. T.
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Lu, J. H.
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Cheng, H. C.
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Chu, F. T.
In this study, excimer laser crystallization (ELC) of amorphous Si1-xGex (a-Si1-xGex) thin film has been demonstrated. A-Si1-xGex thin films with several Ge atomic concentrations were crystallized with different laser energy densities and laser shot numbers per unit area. According to the AES analysis results, the atomic concentration of Ge atom increased gradually toward the surface of the poly-Si1-xGex thin film after excimer laser irradiation. This would lead to the degraded electrical characteristics of the poly-Si1-xGex TFTs. Therefore, a novel Ge doping method has been proposed to fabricate high-performance poly-Si1-xGex TFTs. For small size TFTs, the hole mobility of the poly-Si1-xGex, TFTs was superior to that of poly-Si TFTs. The poly-Si0.91Ge0.09 TFT exhibited a high hole mobility of 112 cm(2)/V-s, while the hole mobility of the poly-Si counterpart was 73 cm(2)/V-s.
Formation of thin-film transistors with a polycrystalline hetero-structure channel layer
(2008-08-01)
Juang, Miin-Horng
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Tsai, I-Shen
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Jang, S-L
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Cheng, H. C.
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電子工程學系及電子研究所
A thin-film transistor (TFT) with a polycrystalline Si/SiC hetero-structure channel layer has been proposed. For the conventional polycrystalline silicon (poly-Si) channel layer, the leakage current would be considerably increased with increase of the negative gate bias voltage. However, when a polycrystalline Si/SiC stacked channel layer is employed, the leakage current exhibits just a slight increase with increase of the negative gate bias voltage. As a result, the leakage current can be largely suppressed to a low level without degrading the on-state current. Moreover, when the channel length is further scaled down to 1 mu m and the gate oxide is reduced to 60 nm thickness, the conventional poly-Si TFT device shows even more obvious deterioration of the leakage current. Instead, for the TFT device with a polycrystalline Si/SiC channel layer, no considerable degradation of the leakage characteristics is caused.
Growth and Field Emission Characteristics of Pillar-like Carbon Nanotubes Using Co-Ti/Al Co-deposited Catalysts at Low Temperature
(2010)
Chang, C. T.
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Lee, C. Y.
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Lin, K. C.
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Lai, R. L.
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Tsai, Wan-Lin
In this essay, the pillar-like CNT field emission arrays synthesis with co-deposited catalysts at low temperature (550 degrees C) was proposed. Pillar-like CNT has been successfully synthesized by thermal CVD system. The current density of this proposed pillar like CNTs was as high as 1272 mu A/cm(2) at 6 V/mu m and the turn-on field was 3.6 V/mu m. Additionally, the reliability was more stable as lower than 7% degradation of initial current density.
Improved Field Emission Characteristics with different Electrode Materials by forming process in a Quasi-planar Thin Film Field Emission Diode
(2010-01-01)
Chang, C. T.
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Hsu, Y. Y.
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Lin, K. C.
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Tsai, Wan-Lin
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Chien, Yun-Shan
The essay was reported the different electrode materials in a quasi-planar thin film field emission diode by different forming process. The forming process causes an increased surface roughness of emitters or reduced the work function of the emitter and results in a higher field enhancement factor, which shows better field emission characteristics. The turn on voltage could from 15 V to 8 V and 6.5V with Co and Pd electrode at the emission current of 100 nA for samples.
Low repetition rate and broad frequency tuning from a grating-coupled passively mode-locked quantum dot laser
(2013-11-18)
Cheng, H. C.
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Wu, Q. Y.
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Pan, C. H.
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Lee, C. P.
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Lin, G.
Passively mode-locked quantum dot lasers with a grating-coupled external cavity arrangement are investigated. A broad repetition-rate tuning range of fundamental mode-locking from 2GHz to a record-low frequency of 79.3 MHz is achieved with selecting the wavelength at 1.28 mu m. A narrow RF linewidth of similar to 25 Hz and an intrinsic linewidth as low as 0.15 Hz are also obtained. (C) 2013 AIP Publishing LLC.
Relaxation-free strained SiGe with super anneal for 32nm high performance PMOS and beyond
(2006)
Yu, Ming H.
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Li, J. H.
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Lin, H. H.
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Chen, C. H.
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Ku, K. C.
The interaction of epitaxially strained SiGe and super annealing or millisecond anneal in high performance PFET fabrication was, for the first time, systematically investigated. When super annealing was applied, the quality of SiGe/Si interface, affected by subsequent ion implantation and post-SiGe thermal treatment, played an important role in SiGe strain relaxation incurring channel stress loss and defect injection to Si substrate resulting in high junction leakage. Defect injection mechanism was proposed to explain the defect formation in Si substrate. The new processing scheme, which preserved SiGe as relaxation-free and avoided defect injection, was developed and for 32nm technology. The device performance gain with 10% Id,sat increment resulting from fully strained SiGe was achieved.
Study of ultra-shallow p(+)n junctions formed by excimer laser annealing
(2010-09-01)
Juang, Miin-Horng
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Lu, C. N.
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Jang, S. L.
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Cheng, H. C.
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電子工程學系及電子研究所
Excellent ultra-shallow p(+)n junctions have been formed by thermally treating the BF(2)(+)-implanted Si samples by excimer laser annealing (ELA) at 300-400 rnJ cm(-2) with post low-temperature long-time furnace annealing (FA) at 600 degrees C. A junction with a leakage current density lower than 20 nA cm(-2) and a sheet resistance smaller than 200 Omega square(-1) can be well achieved. No considerable dopant diffusion is observed by using this low-thermal-budget annealing process. However, by simply using the ELA treatment at 300-400 mJ cm(-2), the resultant junction shows a leakage current density as high as 10(4) nA cm(-2) and a peripheral leakage current density of 10(3) nA cm(-1). The large junction leakage is primarily due to the leakage current generated within the junction region near the local-oxidation-of-silicon (LOCOS) edge, and which is substantially caused by the ELA treatment. The large peripheral junction leakage current density can be significantly reduced to be about 0.2 nA cm(-1) after a post low-temperature FA treatment at 600 degrees C. As a result, the scheme that employs ELA treatment with post low-temperature FA treatment would be efficient for forming excellent ultra-shallow p(+)n junctions at low thermal budget. (C) 2010 Elsevier BM. All rights reserved.
The Strained-SiGe Relaxation Induced Underlying Si Defects Following the Millisecond Annealing for the 32 nm PMOSFETs
(2012)
Yu, M. H.
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Wang, L. T.
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Huang, T. C.
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Lee, T. L.
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Cheng, H. C.
The formation of the induced defects in the underlying Si substrate from the interaction of the partly relaxed source/drain strained-SiGe layer and subsequent millisecond annealing (MSA) have been systematically explored. It could be found that implantation in the shallower region of the strained-SiGe layer did not form defects in the underlying Si because the remaining strained-SiGe layer was sufficiently thick to resist wafer bending in response to the MSA thermal stress. However, deeper medium-level implantation indeed destroyed the part of the pseudomorphic strained-SiGe and the remaining strained-SiGe was too thin to withstand a significantly compressive stress induced by MSA surface heating and larger coefficient of thermal expansion (CTE) for SiGe than it for Si. Then brittle silicon substrate suffered a great tensile stress to generate numerous defects into plastic deformation. During MSA cooling, the over-bending of the surface SiGe layer contracted more than Si substrate and further results in highly tensile bending. Consequently, high defect density in the underlying Si results in high junction leakage and wafer bending leads to photolithographic limitation. A new approach for modifying the implantation conditions was developed to achieve a relaxation-less strained-SiGe layer and defect-free underlying Si substrate for the 32 nm PMOSFETs. (C) 2011 The Electrochemical Society. [DOI: 10.1149/2.017203jes] All rights reserved.
UV photodetectors with lateral self-assembled ZnO nanowires grown at low temperature
(2009)
Yang, P. Y.
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Lee, I. C.
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Chang, C. T.
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Lin, K. C.
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Wang, J. L.
In this paper, a self-assembled lateral growth of ZnO nanowire (NW) photodetector has been successfully synthesized by an aqueous solution method at low temperature (85 degrees C). The growth of ZnO NWs on a silicon substrate with a ZnO seeding layer exhibits single-phase wurtzite ZnO crystal structure, and grows along the c-axis direction. Furthermore, we have demonstrated the current-voltage characteristics and photoresponse of the ZnO NWs with and without UV (325 nm) illumination. Therefore, this low-temperature and simple fabrication process is a viable processing technique to selectively grow lateral ZnO NWs on a flat substrate of any material, with potential applications in flexible NW devices.