Browsing by Author "Cheng, HC"

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A comparative study of Ar and H-2 as carrier gases for the growth of SiC films on Si(100) by electron cyclotron resonance chemical vapor deposition at low temperature
(2001-11-01)
Lee, WH
;
Lin, JC
;
Lee, C
;
Cheng, HC
;
Yew, TR
Electron cyclotron resonance chemical vapor deposition (ECR-CVD) of SiC films from silane and methane gas mixtures at low temperature has been investigated using two different carrier gases, namely, argon and hydrogen. The results obtained are compared. The chemical composition and crystalline microstructure were investigated by Fourier transform infrared spectroscopy (FTIR) and cross-sectional transmission electron microscopy (XTEM), respectively. The results indicate that the carrier gases have a greater influence on the film composition and microstructure as compared to the growth parameters like pressure, power and flow ratio. The deposition mechanism which controls the film characteristics is also presented. (C) 2001 Elsevier Science B.V. All rights reserved.
A novel device structure for low-temperature polysilicon TFTs with controlled grain growth in channel regions
(2000)
Cheng, LJ
;
Lu, YL
;
Lin, CW
;
Chang, TK
;
Cheng, HC
In this paper, we demonstrate a novel device structure of low-temperature polysilicon thin-film transistors (LTPS TFTs) for AMLCD applications with using excimer-laser crystallization (ELC). The device structure consists of a thin channel and a thick source/drain. This structure has its merit in the process of ELC and is capable of improving TFTs' electrical characteristics. During excimer laser irradiation, this kind of recessed structure is able to build up localized lateral thermal gradients in the regions near the steps and entice crystallization from the chiller thick source/drain regions toward the hotter thin channels. Because of the development of crystallization process, the average field-effect mobility of the devices can be increased to about 350 cm(2)/V.s, and the on/off current ratios exceed eight orders. In addition to improvement of device performance, the process window of ELC is broadened with the recessed structure.
A novel germanium doping method for fabrication of high-performance p-channel poly-Si1-xGex TFT by excimer laser crystallization
(2003-04-01)
Chang, TK
;
Chu, FT
;
Lin, CW
;
Tseng, CH
;
Cheng, HC
In this letter, a novel process for fabricating p-channel poly-Si1-xGex thin-film transistors (TFTs) with high-hole mobility was demonstrated. Germanium (Ge) atoms were incorporated into poly-Si by excimer laser irradiation of a-Si1-xGex/poly-Si double layer. For small size TFTs, especially when channel width/length (W/L) was less than 2 mum/2 mum, the hole mobility of poly-Si1-xGex TFTs was superior to that of poly-Si TFTs. It was inferred that the degree of mobility enhancement by Ge incorporation was beyond that of mobility degradation by defect trap generation when TFT size was shrunk to 2 mum/2 mum. The poly-Si0.91Ge0.09 TFT exhibited a high-hole mobility of 112 cm(2)/V-s, while the hole mobility of the poly-Si counterpart was 73 cm(2)/V-s.
A novel laser-processed self-aligned gate-overlapped LDD poly-Si TFT
(2002-03-01)
Lin, CW
;
Tseng, CH
;
Chang, TK
;
Lin, CW
;
Wang, WT
A novel process for fabricating self-aligned gate-overlapped LDD (SAGOLDD) poly-Si thin film transistors (TFTs) was demonstrated. Laser Irradiation for dopant activation was performed from the backside of the quartz wafer. The graded LDD structure was naturally formed under the gate edges due to the lateral diffusion of the dapants during the laser activation. In comparison with the conventional laser-processed self-aligned poly-Si TFTs, the SAGOLDD poly-Si TFTs exhibited lower leakage current, suppressed kink effect, and higher reliability. Moreover, the proposed process was simple and very suitable for low-temperature process.
A novel process to form cobalt silicided p(+) poly-Si gates by BF2+ implantation into bilayered CoSi/a-Si films and subsequent anneal
(1998-07-01)
Lai, WK
;
Liu, HW
;
Juang, MH
;
Chen, NC
;
Cheng, HC
A novel process that implants BF2+ ions into thin bilayered CoSi/a-Si films has been shown to form cobalt silicided pf poly-Si gates with excellent gate oxide integrity and very small flatband shift. The effects of not only using the CoSi layer as an implantation barrier but also keeping the a-Si underlayer during the initial silicide formation both significantly suppress the boron penetration through thin gate oxide.
A novel technology to reduce the antenna charging effects during polysilicon gate electron-cyclotron-resonance etching
(1996-07-01)
Cheng, HC
;
Kang, TK
;
Ku, TK
;
Dai, BT
;
Chen, LP
A novel technique, which uses Cl-2/O-2 mixed gas in the electron cyclotron resonance (ECR) etching system, has been proposed to remove the antenna charging effect of the MOS capacitors with 5-nm-thick oxides during polysilicon gate etching. The Cl-2/O-2 can cause the trenching effect and prevents the gate oxide from the charging damage. Furthermore, the ECR system can provide high polysilicon/oxide selectivity so that the Si substrate under gate oxide is not directly bombarded by the ions. Consequently, the E(bd) degradation of the MOS capacitors disappears as the trenching effect is apparent by using moderate Cl-2/O-2 mixed gas.
A novel two-step etching to suppress the charging damages during metal etching employing helicon wave plasma
(1998-06-01)
Cheng, HC
;
Lin, W
;
Kang, TK
;
Perng, YC
;
Dai, BT
A two-step etching has been performed to eliminate the plasma charging damages during helicon-wave plasma metal etching without selectivity loss, This technique utilized a normal etching recipe to remove the Al film and followed by an optimized etching recipe for the overetching step. By increasing the bias power and decreasing the source power, the optimum etching recipe can cause the plasma more directionally and reduce the Al charging damages. Eventually, the damage mechanism was also reported.
A source-follower type analog buffer using poly-Si TFTs with large design windows
(2005-11-01)
Tai, YH
;
Pai, CC
;
Chen, BT
;
Cheng, HC
;
電子工程學系及電子研究所
New simple source follower circuits using low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) as analog buffers for the integrated data driver circuit of active-matrix liquid crystal displays and active-matrix light emitting diodes are discussed. In addition to the threshold voltage difference of driving TFTs, the unsaturated of output voltage arisen from the significant subthreshold current will also result in the difficulty of the buffer circuit design. The proposed circuit is capable of minimizing the variation from both the signal timing and the device characteristics.
An investigation of bias temperature instability in hydrogenated low-temperature polycrystalline silicon thin film transistors
(2002-09-01)
Lin, CW
;
Tseng, CH
;
Chang, TK
;
Chang, YH
;
Chu, FT
The instability mechanisms of the hydrogenated n-channel low-temperature polycrystalline silicon thin film transistors under on-state stress were investigated with various bias stress conditions and device channel widths. It was found that hot carrier degradation which originated from a high drain electric field and self-heating during high current operation were the two dominant mechanisms responsible for device degradation. An electrically reversible depassivation/passivation phenomenon was also found in devices under high current stress. but not in those under hot carrier stress. It was inferred that the self-heating effect would accelerate the bond breakage and diffusion of hydrogen ions, thus enhancing the rate of depassivation/passivation. Moreover. when the Current in the hot carrier stress mode was sufficiently high. self-heating became the dominant degradation mechanism and hot carrier degradation phenomenon was also suppressed for devices with large channel width, Meanwhile, the electrically reversible depassivation/passivation phenomenon also occurred in this case.
Antenna charging effects on the electrical characteristics of polysilicon gate during electron cyclotron resonance etching
(1996-02-01)
Kang, TK
;
Ueng, SY
;
Dai, BT
;
Chen, LP
;
Cheng, HC
The nonuniformity of the induced leakage current in metal oxide semiconductor (MOS) capacitors has been investigated in an electron cyclotron resonance (ECR) system. For plasma-etched MOS capacitors with 5-nm-thick oxides, it is found that the leakage currents induced by plasma etching increase with increasing overetching time. However, additional E(bd) (breakdown held) degradation is not obvious as overetching percentage increases from 10% to 50%. A mechanism based on the antenna charging effect has been proposed to explain the E(bd) electrical characteristics. In accordance with the mechanism, the E(bd) degradation has been significantly reduced by first etching off a narrow peripheral edge around the gate pattern.
Au/Ge/Pd ohmic contacts to n-GaAs with the Mo/Ti diffusion barrier
(1996-12-01)
Chai, CY
;
Huang, JA
;
Lai, YL
;
Wu, JW
;
Chang, CY
The influences of the As-outdiffusion and Au-indiffusion on the performances of the Au/Ge/Pd/n-GaAs ohmic metallization systems are clarified by investigating three different types of barrier metal structures Au/Ge/Pd/GaAs, Au/Ti/Ge/Pd/GaAs, and Au/Mo/Ti/Ge/Pd/GaAs. The results indicate? that As-outdiffusion leads to higher specific contact resistivity, whereas Au-indiffusion contributes to the turnaround of the contact resistivity at even higher annealing temperature. For Au/Mo/Ti/Ge/Pd/n-GaAs samples, they exhibit the smoothest surface and the lowest specific contact resistivity with the wildest available annealing temperature,range, Moreover, Auger electron spectroscopy depth profiles show that the existing Ti oxide for the Mo/Ti bilayer can very effectively retard Au-indiffusion, reflecting the onset of the turnaround point at much higher annealing temperature.
Characteristics of (Pb, Sr)TiO3 films post treated by low temperature technologies
(2004)
Wang, JL
;
Jan, CK
;
Shye, DC
;
Kuo, MW
;
Cheng, HC
The novel annealing technologies, rapid thermal annealing (RTA) and excimer laser annealing (ELA) at low substrate temperature (300degreesC), were applied on the (Pb, Sr)TiO3 (PSrT) films. The PSrT film post treated by ELA only exhibits ferroelectric property and lager dielectric constant than as-deposited PSrT film. The PSrT film post treated by RTA only shows poor P-E curve and large leakage current. Interesting, the electrical properties of the PSrT film can be greatly enhanced by both of the ELA and the succeeding RTA treatments, so ferroelectric properties and dielectric constant can be reached as high as 15 muC/cm(2) of P-s and 574 of dielectric constant. In this work, excellent electrical properties of PSrT film post treated by both of ELA and succeeding RTA at low substrate temperature were systematically studied.
Characteristics of low-temperature-prepared (Ba, Sr)TiO3 films post treated by novel excimer laser annealing
(2002)
Shye, DC
;
Chiou, BS
;
Hwang, CC
;
Chen, JS
;
Su, IW
Thin (Ba0.5Sr0.5)TiO3 (BST) films were sputtered on Pt[FiN/Ti/Si multilayer substrates at very low temperature (150degrees C). A novel process, using wavelength 248-nm KrF excimer laser annealing (ELA), has been undertaken to implement barium strontium titanate (BST) films at a low process temperature of 300degrees C. The crystallinity and dielectric constant are greatly improved after ELA treatment. In this work, the variation of texture was investigated. Besides, the escaped oxygen atoms from BST films were detected in-situ using a residual gas analyzer (RGA) during ELA process. Thus, the degradation of upper surface is strongly influenced by the laser energy fluence for an ELA-BST film.
Characterization and fabrication of chimney-shaped metal field emitters
(1996-01-01)
Cheng, HC
;
Wang, CC
;
Ku, TK
;
Hsieh, IJ
;
電子工程學系及電子研究所
A novel fabrication technology has been successully developed for chimney-shaped metal field emitters in order to improve the electrical characterisitcs of field-emission devices. This technology is based on anisotropic dry etching and sputtering deposition of metal film as well as wet etching of the attached silicon. It enables easy fabrication of chimney-shaped field emitters with excellent uniformity and high reproducibility. The anode current of the chimney-shaped Cr field emitter array (FEA) is 36.3 mu-A at the applied voltage of 1100 V and the threshold voltage V-T, defined as that for which the anode current I-n reaches 1 mu-A is 787 V. The chimney-shaped Cr FEA emits a current thirty times higher than that from the cone-shaped Cr-clad FEA at the applied voltage of 1100 V. This can be attributed to the presence of many sharp tips along the edge of the chimney-shaped emitter. The degradation phenomenon is not observed because compensation occurs between these many sharp tips. Another merit of this technique is that only one photolithography mask is needed during processing.
Characterization of anodic aluminum oxide film and its application to amorphous silicon thin film transistors
(1996-02-01)
Liang, CW
;
Luo, TC
;
Feng, MS
;
Cheng, HC
;
Su, D
AL(2)O(3)/SINx double-layered dielectric films suitable for large-size amorphous silicon thin film transistor liquid crystal displays (a-Si:H TFT LCD) have been prepared by anodization and plasma enhanced chemical vapor deposition (PECVD). Al2O3 films were formed at various pH values and volume ratio of water (H2O%) in the electrolyte. The optimal quality of Al2O3 film was achieved at pH = 6 and H2O% = 30. These high-quality Al2O3 films have denser structure, lower etching rate (90 Angstrom min(-1)) and smooth surface morphology after etching. The capacitors made of the anodization show a breakdown field as high as 7.8 MV cm(-1) and a low leakage current density of 10 nA cm(-2) at a dielectric field of 3 MV cm(-1). Furthermore, a-Si:H TFTs with Al gate and different gate dielectrics (Al2O3/SINx and SiNx) were also fabricated and evaluated. The TFTs with Al2O3/SiNx double-layered gate dielectric provide better performances, such as the smaller threshold voltage (1.76 V), improved subthreshold swing (1.0 V dec(-1)), and lower off-current (3.8 PA) than those of the device with single SiNx, film.
Characterization of GaN epitaxial layers on SiC substrates with AlxGa1-xN buffer layers
(1997-12-18)
Lin, CF
;
Cheng, HC
;
Feng, MS
;
Chi, GC
;
材料科學與工程學系
High quality GaN epitaxial layers were obtained with AlxGa1-xN buffer layers on 6H-SiC substrates. The low-pressure metalorganic chemical vapor deposition (LP-MOCVD) method was used. The 500 Angstrom thick buffer layers of AlxGa1-xN (0 less than or equal to x less than or equal to 1) were deposited on SiC substrates at 1025 degrees C. The FWHM of GaN (0004) X-ray curves are 2-3 arcmin, which vary with the Al content in AlxGa1-xN buffer layers. An optimum Al content is found to be 0.18. The best GaN epitaxial film has the mobility and carrier concentration about 564 cm(2) V-1 s(-1) and 1.6 x 10(17) cm(-3) at 300 K. The splitting diffraction angle between GaN and AlxGa1-xN were also analyzed from X-ray diffraction curves. (C) 1997 Elsevier Science S.A.
Characterizing trench-gate power metal-oxide-semiconductor field effect transistor with multi-layer dielectrics at the trench bottom
(2003-11-01)
Lin, MJ
;
Liaw, CW
;
Chang, FL
;
Cheng, HC
;
電子工程學系及電子研究所
Power devices with a high switching speed and a low conduction resistance are crucially important in power conversion circuits. In this study, a trench-gate power metal-oxide-semiconductor field effect transistor (MOSFET) with a high-density cell design 20.6 Mcell/cm(2) was implemented for the first time using multilayer dielectrics with an oxide-nitride-oxide (ONO) structure at the bottom of the trench. The thick ONO dielectric layers at the bottom of the trench compensate for the increase in Miller capacitance per unit area as the cell density increases. The resulting device exhibits excellent characteristics of gate charge, switching power loss, gate oxide quality and practical process stability, superior to those of the conventional structure. An n-channel 25.8 V trench gate MOSFET with a specific on-resistance of 0.15 mOmegam(2), and R-ON x Q(GD) figure-of-merit 41 mOmega.nC is presented.
Charging damages to gate oxides in a helicon O-2 plasma
(1997-12-01)
Lin, W
;
Kang, TK
;
Perng, YC
;
Dai, BT
;
Cheng, HC
After the exposure of metal oxide semiconductor (MOS) capacitors with antenna structures to the helicon O-2 plasma, the leakage current. charge-to-breakdown (Q(bd)) and capacitance-voltage (C-V) curves have been characterized to realize the charging damages. The results indicate that the quasi static C-V(QSCV) distortion and Q(bd) depend on the exposure time rather than the antenna ratio. The QSCV and Q(bd) Show a two stage degradation as the exposure time increases. The leakage current increases slightly for the specimens exposed to the plasma for less than 120 s, and increases considerably for the ones with the exposure time of 300 s. Based on these results, the degradation mechanism of gate oxides under the helicon O-2 plasma is established.
Charging damages to gate oxides in a helicon O-2 plasma
(1997-12-01)
Lin, W
;
Kang, TK
;
Perng, YC
;
Dai, BT
;
Cheng, HC
After the exposure of metal oxide semiconductor (MOS) capacitors with antenna structures to the helicon O-2 plasma, the leakage current. charge-to-breakdown (Q(bd)) and capacitance-voltage (C-V) curves have been characterized to realize the charging damages. The results indicate that the quasi static C-V(QSCV) distortion and Q(bd) depend on the exposure time rather than the antenna ratio. The QSCV and Q(bd) Show a two stage degradation as the exposure time increases. The leakage current increases slightly for the specimens exposed to the plasma for less than 120 s, and increases considerably for the ones with the exposure time of 300 s. Based on these results, the degradation mechanism of gate oxides under the helicon O-2 plasma is established.
Chimney-shaped and plateau-shaped gate electrode field emission arrays
(1998)
Tarntair, FG
;
Wang, CC
;
Hong, WK
;
Huang, HK
;
Cheng, HC
A triode structure of chimney-shaped field emitter arrays is proposed in this article. This triode structure includes the chimney-shaped emitter, thermal oxidation dioxide, and the plateau-shaped singlecrystalline silicon gate electrode. For the application of the matrix-addressable and large area flat panel display, the uniform structure of the emitters and the yield become critical manufacturing issues when attempting to control nano-meter size features. The uniformity and yield of the chimney-shaped emitters are very well controlled. The nano-sized gate-to-emitter separations can be created by the changing thickness of the insulator. The uniformity of the insulator and emitter material can be controlled within 3% which can be obtained by most large area thin film deposition tools, not by photolithography.