Browsing by Author "Cheng, HW"

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A content-based methodology for power-aware motion estimation architecture
(2005-10-01)
Cheng, HW
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a novel power-aware motion estimation algorithm, called adaptive content-based subsample algorithm (ACSA), for battery-powered multimedia devices. While the battery status changes, the architecture adaptively performs graceful tradeoffs between power consumption and compression quality. As the available energy decreases, the algorithm raises the subsample rate for maximizing battery lifetime. Differing from the existing subsample algorithms, the content-based algorithm first extracts edge pixels from a macro-block and then subsamples the remaining low-frequency part. In this way, we can alleviate the aliasing problem and thus keep the quality degradation low as the subsample rate increases. As shown in experimental results, the architecture can dynamically operate at different power consumption modes with little quality degradation according to the remaining capacity of battery pack while the power overhead of edge extraction is under 0.8%.
A content-based motion estimation algorithm for power-aware architecture
(2003)
Cheng, HW
;
Dung, LR
;
Yen, JH
;
Wang, JJ
;
電控工程研究所
This paper presents a novel power-aware architecture, called the vario-power architecture, for motion estimation. Based on the proposed content-based subsample algorithm, the architecture can operate at different power consumption modes with little quality degradation and the switching of power mode can be done dynamically. As shown in the simulation results, the power consumption can be significantly reduced by simply change the threshold parameters while the quality degradations are little.
A novel vario-power architecture of motion estimation using a content-based subsample algorithm
(2003)
Cheng, HW
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
Motion estimation is a key element in many video compression systems which tends to dominate computational and hence power requirements. With increasing demand of portable, power-aware multimedia devices, an architecture that can be flexible in both power consumption and compression quality is highly required. To meet the requirement, this paper presents a novel power-aware architecture, called the vario-power architecture, for motion estimation. Based on a semi-systolic array with content-based subsample algorithm, the architecture dynamically disable some processing elements to reduce the power consumption. By performing the edge extraction first, a threshold was then set as the criterion of whether to enable/disable processing elements and thus the switch activities of system can be reduced. As the result, the architecture may dynamically operate at different power consumption modes according to the remaining capacity of battery pack with little quality degradation.
A vario-power ME architecture using content-based subsample algorithm
(2004-02-01)
Cheng, HW
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
The Motion estimator is a key element in many video compression systems and it tends to dominate the power consumption in them. With increasing demand of portable, power-aware multimedia devices, an architecture that can be flexible in both power consumption and compression quality is essential. To meet this requirement, this paper presents a novel power-aware architecture, called the Vario-Power Architecture, for the motion estimation. Based on a semi-systolic array with the content-based subsample algorithm, the architecture real-time disables some processing elements to reduce power consumption. By performing the edge extraction first, a threshold is then set as the criterion of whether to enable or disable processing elements and thus the switch activities of the system can be reduced. As the simulation shows, the architecture may operate at different power consumption modes according to the remaining capacity of the battery pack, giving little quality degradation and the power overhead under 0.36%.(1)
EFBLA: a two-phase matching algorithm for fast motion estimation
(2004-05-27)
Cheng, HW
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
A novel motion estimation algorithm that contains edge matching and block matching is presented. The edge matching reduces candidates for the block matching that performs accurate searching. Thus, the two-phase procedure speeds up motion estimation. As a result, edge-matching first block-matching last algorithm (EFBLA) may significantly save the computation load by 93.9%.
EFBLA: A two-phase matching algorithm for fast motion estimation
(2002)
Cheng, HW
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a novel matching algorithm for fast motion estimation. The algorithm, called the Edge-matching First Block-matching Last Algorithm (EFBLA), first employs the edge-matching procedure to determine candidate motion vectors and then performs the conventional block matching with the SAD criteria on the candidates. The edge-matching procedure features low computation load and high degree of data reusability; therefore, it requires fewer operations and lower memory size compared with the full search algorithm. As the result of benchmarking and comparing to the full search algorithm, EFBLA may significantly save the computation load by 93.9% while the degradation of PSNR is very little.