Browsing by Author "Cheng, Hao-Chung"

Now showing 1 - 7 of 7

A Fully Integrated Light-Powering System with Integrated CMOS Photovoltaic Cell for Batteryless IoT Devices
(2019-01-01)
Chen, Po-Han
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Huang, Chao-Yi
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Cheng, Hao-Chung
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Chen, Po-Hung
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電子工程學系及電子研究所
This paper presents a fully integrated CMOS lightpowering system, integrating CMOS photovoltaic cell and energy harvesting interface, for batteryless internet of things (IoT). The CMOS photovoltaic cell employs deep N-well (DNW) based structure to improve the light-electric conversion efficiency. The energy harvesting interface utilizes a fully integrated two-stage switched-capacitor dc-dc converter to provide an appropriate output voltage for load circuits. It provides 1 V and 0.9 - 1.1 V output under light load and heavy load, respectively. The chip is designed and fabricated by 180-nm CMOS process, without using any off-chip components, except a storage capacitor for testing. The experimental results demonstrate that the proposed 1mm x 2mm fully integrated light-powering system can periodically provide 0.9 V to 1.1 V output voltage to power 1-mA loading circuit. The proposed interface achieves 70 percent peak-efficiency at 1 mu A and higher than 60 percent efficiency over 0.5 mu A to 2 mu A loading currents.
A Fully Integrated Step-Down Switched-Capacitor DC-DC Converter With Dual Output Regulation Mechanisms
(2020-09-01)
Chen, Po-Han
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Cheng, Hao-Chung
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Chen, Po-Hung
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This letter proposes a fully integrated step-down switched-capacitor (SC) DC-DC converter using 0.18-mu m CMOS technology for system-on-chip applications. The proposed stepdown switched-capacitor DC-DC converter used two control mechanisms: the switch array modulation technique to regulate the output voltage and the voltage ripple modulation technique to adjust the output voltage ripple of the converter as the loading current varied. As a result, the proposed converter could generate a regulated output voltage with low voltage ripple. The converter core performed at conversion ratios of 1/3 and 1/2 under an input voltage of 1.8 V. The measurement results on 180-nm technology showed that the proposed fully integrated step-down switched-capacitor DC-DC converter could achieve a peak power conversion efficiency of 74.1% and maintain power conversion efficiency at levels over 70% within loading ranges between 1.4 and 5 mA. The output voltage ripple was controlled at levels under 63.4 mV within a loading current ranging between 0.1 and 5 mA.
A Single-Inductor Triple-Source Quad-Mode Energy-Harvesting Interface With Automatic Source Selection and Reversely Polarized Energy Recycling
(2019-10-01)
Chen, Po-Hung
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Cheng, Hao-Chung
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Lo, Chih-Lun
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a single-inductor triple-source quad-mode (SITSQM) energy-harvesting interface in a 0.18-mu m CMOS process. The proposed reversely polarized energy recycling (RPER) technique improves not only the conversion efficiency at low input voltage but also the system's output power range. The interface employs the buck-boost topology to convert energy from photovoltaic (PV) cells and a thermoelectric generator (TEG) to a regulated 1.2-V output. The proposed converter features four different operating modes, namely, harvesting, recycling, storing, and backup. The operating mode is automatically selected according to the input and load conditions using the automatic source selection mechanism. The experimental results demonstrate 25.3% efficiency improvement and 10x output power range extension from the proposed RPER technique. The proposed SITSQM converter automatically manages three harvesting sources with 82.1% peak conversion efficiency.
A Tri-Mode Fully-Integrated Capacitive Voltage Multiplier for Photovoltaic Energy Harvesting
(2017-01-01)
Cheng, Hao-Chung
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Lin, Min-Yen
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Chen, Po-Hung
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a tri-mode fully-integrated capacitive voltage multiplier is proposed. The system provides power conversion efficiency over 60% within the loading current ranges from 60 mu A to 160 mu A. The input voltage (V-IN) ranges from 0.45-0.7V to meet the output of photovoltaic cells, and the output voltage (V-OUT) is set as 1.2V. The proposed tri-mode operation combines doubler mode, tripler mode and boosting mode to cover wide input voltage range. The doubler mode is implemented by utilizing a single-stage charge pump (CP) circuit while the tripler mode is realized by connecting two CP stages in series. The boosting mode enlarges the gate swing of the second CP power stage to further reduce the conduction loss of the power transistors, which allows the system to operate at 0.45-V V-IN. The regulation controller consists of the coarse/fine modulators and mode selection circuit. By applying the proposed regulation and reconfigurable techniques, the system is able to switch operating mode automatically as input voltage varies. To achieve low power and low voltage operation, all regulation systems are built by digital circuits. From simulation results, the peak power conversion efficiency of 89% is achieved at 100-mu A output current.
An 82.1%-Power-Efficiency Single-Inductor Triple-Source Quad-Mode Energy Harvesting Interface with Automatic Source Selection and Reversely Polarized Energy Recycling
(2018-01-01)
Lo, Chih-Lun
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Cheng, Hao-Chung
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Liao, Pei-Chun
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Chen, Yi-Lun
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Chen, Po-Hung
In this paper, a single-inductor triple-source quad mode energy harvesting interface with automatic source selection is developed for multi-source energy harvesting. The interface employs buck-boost topology to convert the energy from photovoltaic (PV) cells and thermoelectric generator (TEG) to a regulated 1.2-V output. The proposed converter has four operating modes: harvesting mode (BM), recycling, mode (RM), storage mode (SM), and backup mode (BM). The operating mode is selected automatically according to the input and load conditions to appropriately transfer the energy. The proposed reversely polarized energy recycling (RPER) technique extends the available output power range by 10x with 25.3% efficiency improvement at low input voltage. The measurement results demonstrates the proposed interface achieves the peak efficiency of 82.1%.
An Optically-Powered 432 MHz Wireless Tag for Batteryless Internet-of-Things Applications
(2019-09-01)
Cheng, Hao-Chung
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Chen, Yen-Ting
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Chen, Po-Hung
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Liao, Yu-Te
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電子工程學系及電子研究所
This paper presents an optically-powered wireless tag, integrating a charge pump (CP) and a low-power RF transmitter for batteryless Internet-of-Things (IoT) applications. The proposed charge pump with hysteresis regulation mechanism (HRM) powers the transmitter circuit using indoor light energy. The charge pump enables the transmitter whenever the output capacitor stores sufficient energy and guarantees a short period signal transmission. The proposed low-power transmitter contains the subharmonically injection-locked PLL and the capacitive coupling technique to achieve a large frequency multiplication ratio. The proposed batteryless wireless chip is fabricated in 0.18-mu m CMOS process. The measurement results demonstrate that the proposed charge pump provides a 1.1 to 1.3 V hysteresis regulated voltage under indoor light illumination larger than 300 lux. The charge pump achieves 84.1% peak efficiency and the communication distance of 3 meters is demonstrated while only consuming 248 mu W.
Automatic Mode-Selected Energy Harvesting Interface With > 80% Power Efficiency Over 200 nW to 10 mW
(2018-12-01)
Chen, Po-Hung
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Cheng, Hao-Chung
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Ai, Yi-An
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Chung, Wang-Ting
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電子工程學系及電子研究所
This paper proposes a dual-mode digital buck converter with an automatic mode-select feature in a 0.18-mu m CMOS for self-powered Internet-of-Things applications. The proposed converter combines the digital pulsewidth modulation and the proposed predetermined pulse-frequency modulation (PPFM) techniques to achieve both a high conversion efficiency and a wide output power range. The proposed PPFM technique calculates the appropriate OFF time of the power transistor in advance, eliminating the additional power budget requirement of the conventional zero-crossing detection circuit. From the results, it can be seen that the conversion efficiency improves by 21% under ultralight-load conditions. The available input voltage (V-IN) ranges from 0.55 to 1.8 V for a wide variety of energy harvesters, and the output voltage (V-OUT) ranges from 0.3 to 0.55 V to power the energy-efficient CMOS digital circuits. The proposed dual-mode digital buck converter achieves a maximum conversion efficiency of 90.5%, with an output power ranging from 25 nW to 10 mW. Owing to the proposed PPFM technique, the converter achieves a power conversion efficiency of more than 80%, with an output power of 200 nW to 10 mW.