Browsing by Author "Cheng, Huang-Chung"

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A New Charge-Trap-Engineered Memory Device with Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) Structure for LTPS-TFT-Based Applications
(2010)
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Chen, Sheng-Kai
;
Yu, Ming H.
;
Kang, Tsung-Kuei
For the first time, a new Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) LTPS-TFT-based charge-trapping memory integrated on a gate-all-around field-enhanced-nanowire architecture was demonstrated. The vacuum, simply formed by an in-situ encapsulation, substituted for the traditional tunneling oxide. Due to the lowest-k and empty properties of vacuum, SONVAS features electric field enhancement in tunneling layer and immunity against the creation of interface traps and the charge trapping in the damaged tunneling oxide during P/E cycling, resulting in the much-improved P/E efficiency and reliability, respectively. Therefore, such vacuum-introduced SONVAS memory device with process simplicity is very suitable for the future system-on-panel (SOP) and 3D-stacking flash applications.
A new pixel circuit for driving organic light emitting diodes with low temperature polycrystalline thin film transistors
(2005)
Chen, Bo-Ting
;
Kuo, Yu-Ju
;
Pai, Cheng-Chiu
;
Tsai, Chun-Chien
;
Cheng, Huang-Chung
A new active matrix organic light emitting diode (AM-OLED) pixel circuit design, based on the low-temperature polycrystalline thin-film transistors (LTPS-TFTs) is proposed and verified by SPICE simulation. The voltage-programming pixel circuit is formed by five n-type TFTs. one additional control signal, and a storage capacitor. The simulation results show that this pixel circuit has high immunity to the variation of poly-Si TFT characteristics.
A New Pixel Circuit for Driving Organic Light-Emitting Diode With Low Temperature Polycrystalline Silicon Thin-Film Transistors
(2005-09-01)
Tai, Ya-Hsiang
;
Chen, Bo-Ting
;
Kuo, Yu-Ju
;
Tsai, Chun-Chien
;
Chiang, Ko-Yu
A new pixel circuit design for active matrix organic light-emitting diode (AMOLED), based on the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) is proposed and verified by SPICE simulation. Threshold voltage compensation pixel circuit consisting of four n-type TFTs, one p-type TFT, one additional control signal, and one storage capacitor is used to enhance display image quality. The simulation results show that this pixel circuit has high immunity to the variation of poly-Si TFT characteristics.
A Novel Coaxial-Structured Amorphous-Silicon p-i-n Solar Cell With Al-Doped ZnO Nanowires
(2011-07-01)
Li, Hung-Hsien
;
Yang, Po-Yu
;
Chiou, Si-Ming
;
Liu, Han-Wen
;
Cheng, Huang-Chung
A novel coaxial-structured amorphous-silicon (a-Si) p-i-n solar cell with 1-mu m-long low-temperature hydrothermally synthesized Al-doped-ZnO (AZO) nanowires was demonstrated for the first time. The conversion efficiency. increased from 3.92% to 4.27% when the intrinsic a-Si thickness was increased from 25 to 150 nm and then decreased to 3.66% when the intrinsic layer thickness was further increased to 250 nm. It was attributed to an excessively thick intrinsic a-Si layer that would decrease the internal electrical field and interfere with charge separation. With the optimum intrinsic a-Si thickness of 150 nm, the conversion efficiency increased from 4.27% to 4.73% when the AZO wire length was increased from 1 to 2 mu m. Moreover, the proposed coaxial-structured solar cell exhibited a nearly 46% efficiency enhancement over a conventional a-Si thin-film solar cell.
A Novel LTPS-TFT-Based Charge-Trapping Memory Device with Field-Enhanced Nanowire Structure
(2009)
Liao, Ta-Chuan
;
Chen, Sheng-Kai
;
Yu, Ming H.
;
Wu, Chun-Yu
;
Kang, Tsung-Kuei
A novel gate-all-around low-temperature poly-Si (LIPS) thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carrier tunneling via such a structure led to faster PIE speed and wider memory window for the FEN-TFT SONOS as compared to the conventional planar (CP) counterpart. The improvement was also further verified with the simulation results. Such a high-performance FEN-TFT SONOS memory with process simplicity is very suitable for future system-on-panel (SOP) applications.
A Novel pH Sensor of Extended-Gate Field-Effect Transistors With Laser-Irradiated Carbon-Nanotube Network
(2012-11-01)
Chien, Yun-Shan
;
Tsai, Wan-Lin
;
Lee, I-Che
;
Chou, Jung-Chuan
;
Cheng, Huang-Chung
The extended-gate field-effect transistors (EGFETs) with only the carbon-nanotube (CNT) thin film as both the sensing membrane and the contact electrode have been demonstrated for the first time to exhibit superior pH sensing characteristics. The continuous-wave laser was necessary to improve the pH sensitivity to be 50.9 mV/pH and the linearity values to be 0.9978 for pH = 3 to pH = 13 wide sensing range, respectively. It implied that the laser energy would unzip the chemically modified multiwalled CNTs (MWCNTs) into numerous graphite slices, resulting in the elevated sensing sites and the improved electrical and sensing properties. Therefore, the laser-irradiated MWCNT network is promising for the applications in the flexible and transparent pH-EGFETs.
A Novel Polysilicon Field-Enhanced Nanowire Thin-Film Transistor with the TiN-Hafnia-Nitride-Vacuum-Silicon (THNVAS) Structure for Nonvolatile Memory Applications
(2012-07-01)
Wu, Chun-Yu
;
Liao, Ta-Chuan
;
Liu, Yen-Ting
;
Yu, Ming H.
;
Cheng, Huang-Chung
A novel poly-Si field-enhanced nanowire (FEN) TFT memory with the TiN-hafnia-nitride-vacuum-silicon (THNVAS) structure fabricated simply via a sidewall spacer formation has been presented. The THNVAS devices with superior memory performance were demonstrated by introducing the hafnia as blocking oxide and the vacuum, the lowest-k in nature, as tunneling layer. According to the simulation results, the memory device with oxide/nitride/vacuum gate dielectric exhibited a higher local electric-field of 4.72 x 10(7) V/cm as compared to 2.55 x 10(7) V/cm for the conventional oxide/nitride/oxide counterpart. In addition, the electric-field of tunneling layer could be further increased to 7.06 x 10(7) V/cm while the blocking oxide was substituted for hafnia. The experimental data showed that THNVAS possessed a greater threshold voltage shift of 3.75 V in 10 ms at V-GS = 12 V, whereas the shift only 2.5 V for THNOS ones. These considerable improvements for THNVAS devices could be attributed to the evident field enhancement across the vacuum tunneling layer. Furthermore, owing to the empty feature of vacuum tunneling layer, the THNVAS demonstrated much-improved endurance performance and preferable data retention property. Hence, such excellent characteristics of THNVAS will be an attractive nonvolatile memory for future system-on-panel and 3-D Flash applications.
A Novel Scheme for Fabricating CMOS Inverters With Poly-Si Nanowire Channels
(2012-06-01)
Kuo, Chia-Hao
;
Lin, Horng-Chih
;
Lee, I-Che
;
Cheng, Huang-Chung
;
Huang, Tiao-Yuan
A novel complementary metal-oxide-semiconductor inverter with poly-Si nanowire channels is proposed and demonstrated in this letter. The scheme employs a clever tilted-angle implant process in the fabrication; therefore, the formation of the source and drain of both p-channel and n-channel devices requires only one lithographic step. The fabricated n-channel and p-channel field-effect transistors in the inverters show a high ON/OFF current ratio, an acceptable subthreshold swing, and a symmetric driving current, thus enabling the realization of excellent characteristics of the inverters.
A novel self-aligned field induced drain polycrystalline silicon thin film transistor fabricated by using a selective side etch process
(2007)
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Chien, Feng-Tso
;
Tsai, Chun-Chien
;
Chen, Hsiu-Hsin
A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with vacuum gaps has been proposed and fabricated only with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH4-based passivation oxide under the vacuum process chamber. Experimental results reveal that the proposed T-Gate poly-Si TFTs have excellent electrical performance, which has maximum on-off current ratio of 4.6 x 10(7), and off-state leakage current at V-GS = -10 V and V-DS = 5V of about 100 times less than that of the conventional one. These improvements are attributed to the additional undoped offset region and the vacuum gap, which reduce the maximum electric field at drain junction while the sub-gate maintains the on-current. Therefore, such a T-Gate poly-Si TFT is very suitable for the applications and manufacturing in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs).
A Novel SONOS Memory With Recessed-Channel Poly-Si TFT via Excimer Laser Crystallization
(2012-04-01)
Lee, I-Che
;
Tsai, Chun-Chien
;
Kuo, Hsu-Hang
;
Yang, Po-Yu
;
Wang, Chao-Lung
A silicon-oxide-nitride-oxide-silicon memory with recessed-channel (RC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) via excimer-laser crystallization (ELC) has been demonstrated to achieve a high mobility of similar to 400 cm(2)/V . s and a large ON/OFF current ratio of similar to 10(8). Such a high performance is because the RC poly-Si TFTs possess only one perpendicular grain boundary (GB) in the channel and the corresponding protrusion at this GB. In addition, the proposed devices also exhibited the largest memory window of 2.63 V in 10 ms with respect to 2.37 and 1.31 V for the conventional-ELC and solid-phase-crystallized ones, respectively. Since the silicon grain growth could be artificially controlled, the device-to-device uniformity could be significantly improved. Therefore, such a simple scheme is promising for applications of low-temperature poly-Si TFTs in 3-D ICs and system on panel.
A poly-Si thin-film transistor with the in situ vacuum gaps under the T-shaped-gated electrode
(2006)
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Chien, Feng-Tso
;
Tsai, Chun-Chien
;
Chen, Hsiu-Hsin
A T-shaped-gated (T-gate) poly-Si thin-film transistor (TFT) with symmetric vacuum gaps has been proposed and fabricated simply with a selective-etching technique and an in situ vacuum encapsulation. The proposed TFT has demonstrated a higher maximum on-off current ratio and superior reliability compared to the conventional TFTs. This is attributed to the resulting offset region and vacuum gap to reduce the off-state leakage current and improve the hot-carrier reliability, while the extra subgate serves to induce an inversion layer at the offset region to maintain the on current during the on state. Therefore, such a T-gate poly-Si TFT is very suitable for manufacturing and applications in active-matrix flat panel electronics. (c) 2006 The Electrochemical Society.
A quasi-planar thin film field emission diode
(2007-11-01)
Lin, Kao-Chao
;
Juan, Chuan-Ping
;
Lai, Rui-Ling
;
Chen, Hsia-Wei
;
Syu, Yu-Ying
A novel quasi-planar thin-film field emitter is fabricated by thin-film deposition and wet etching processes. The spacing between the emitters and collectors could be well controlled on the basis of the thicknesses of Cr thin films, which create submicron gaps. A forming process increases emitter surface roughness and results in a higher field enhancement factor, which shows better field emission characteristics. The turn-on voltage (at which the current level is 100 nA) of the device with a Cr thin film thickness of 300 nm is as low as 12 V, and the current fluctuation in I hour test at a driving voltage of 20 V represents a variation from -86 to +114%.
Advanced gate-all-around fin-like poly-Si TFTs with multiple nanowire channels
(2008)
Tu, Shih-Wei
;
Liao, Ta-Chuan
;
Lin, Wei-Kai
;
Liu, Cheng-Chin
;
Tai, Ya-Hsiang
The gate-all-around (GAA) fin-like poly-Si TFTs (FinTFTs) with multiple nanowire channels (MNCs) have been fabricated using a simple process to demonstrate high performance electrical characteristics. The fin-like nanowire (NW) channel with high body thickness-to-width ratio (T-Fin/W-Fin), approximately equals to one, was realized only with a sidewall-spacer formation. The unique suspending MNCs were also achieved to build the GAA structure. By the way, the GAA-MNC Fin TFTs showed outstanding three-dimensional gate controllability and excellent electrical characteristics, which revealed a high ON/OFF current ratio (>10(8)), a low threshold voltage, a steep subthreshold swing, a near-free drain-induced barrier lowering and a good reliability. Therefore, such the high-performance GAA-MNC FinTFTs are vet-v suitable for the applications in the system-on-panel (SOP) and three-dimensional (3D) circuits.
An Extended-Gate Field-Effect Transistor With Low-Temperature Hydrothermally Synthesized SnO2 Nanorods as pH Sensor
(2012-10-01)
Li, Hung-Hsien
;
Dai, Wei-Syuan
;
Chou, Jung-Chuan
;
Cheng, Huang-Chung
;
電子工程學系及電子研究所
An extended-gate field-effect transistor (EGFET) with low-temperature hydrothermally synthesized SnO2 nanorods as the pH sensor was demonstrated for the first time. The SnO2 nanorod sensor exhibited the higher sensitivity of 55.18 mV/pH and larger linearity of 0.9952 in the wide sensing range of pH 1-13 with respect to the thin-film one. The nearly 15% sensitivity enhancement for such a sensor was attributed to the high surface-to-volume ratio of the nanorod structure, reflecting larger effective sensing areas. The characteristics of the output voltage versus sensing time also indicated good reliability and durability for the SnO2 nanorod sensor. Furthermore, the hysteresis was only 3.69 mV after the solution was changed as pH7 --> pH3 --> pH7 --> pH11 --> pH7.
Annealing effect on the photoluminescence characteristics of ZnO-nanowires and the improved optoelectronic characteristics of p-NiO/n-ZnO nanowire UV detectors
(2015-06-01)
Li, Yu-Ren
;
Wan, Chung-Yun
;
Chang, Chia-Tsung
;
Huang, Yu-Chin
;
Tsai, Wan-Lin
Transparent ultraviolet (UV) detectors with nanoheterojunctions (NHJs) of p-type NiO and n-type ZnO nanowires (ZnO-NWs) were successfully fabricated using a DC sputtering system and a hydrothermal process, respectively. After annealing in nitrogen ambient, the near-band-edge emission to deep level emission ratio (NBE/DLE) of ZnO-NWs gradually increased as the temperature increased and reached a maximum of 28.9 at a temperature setting of 500 degrees C. In contrast, after annealing in oxygen atmosphere, the NBE/DLE of ZnO-NWs initially increased from 1.2 to 5.9 and then decreased to 3.2. At a reverse bias of 2V, the devices with the 500-degrees C-N-2-annealed ZnO-NWs exhibited better sensitivity (J(UV)/J(Dark) = 5.65; J(Visible)/J(Dark) = 1.35) to UV light (365 nm, 0.3 mW/cm(2)) than those with the as-grown ZnO-NWs (J(UV)/J(Dark) = 4.98; J(Visible)/J(Dark) = 3.82) because the structural defects in ZnO-NWs were effectively eliminated after annealing in nitrogen ambient at 500 degrees C. (C) 2015 The Japan Society of Applied Physics
Approaching conversion limit with all-dielectric solar cell reflectors
(2015-02-09)
Fu, Sze Ming
;
Lai, Yi-Chun
;
Tseng, Chi Wei
;
Yan, Sheng Lun
;
Zhong, Yan Kai
Metallic back reflectors has been used for thin-film and wafer-based solar cells for very long time. Nonetheless, the metallic mirrors might not be the best choices for photovoltaics. In this work, we show that solar cells with all-dielectric reflectors can surpass the best-configured metal-backed devices. Theoretical and experimental results all show that superior large-angle light scattering capability can be achieved by the diffuse medium reflectors, and the solar cell J-V enhancement is higher for solar cells using all-dielectric reflectors. Specifically, the measured diffused scattering efficiency (D.S.E.) of a diffuse medium reflector is >0.8 for the light trapping spectral range (600nm-1000nm), and the measured reflectance of a diffuse medium can be as high as silver if the geometry of embedded titanium oxide(TiO2) nanoparticles is optimized. Moreover, the diffuse medium reflectors have the additional advantage of room-temperature processing, low cost, and very high throughput. We believe that using all-dielectric solar cell reflectors is a way to approach the thermodynamic conversion limit by completely excluding metallic dissipation. (C) 2015 Optical Society of America
Carbon nanotubes synthesized at low temperature and a novel self-focusing gated field emission device
(2008)
Hsu, Yu-Ying
;
Lin, Kao-Chao
;
Chen, Hsia-Wei
;
Juan, Chuan-Ping
;
Cheng, Huang-Chung
A method for synthesis of CNTs at low temperature using thermal CVD is proposed. A multi-layered catalyst, Co/Ti/Al, has been successfully utilized to synthesize carbon nanotubes at 500 square by thermal CVD via modifying the flow rate of reaction gases. The flow rates of ethylene, hydrogen, and nitrogen are determined to he 125, 10, and 1000 sccm to improve the growth and field emission characteristics of CNTs at low temperature. Moreover, a novel self-focusing gated device was proposed to resolve the problem of electron beam divergence.
Carbon-nanotube-based field emission devices with a self-focusing gate structure
(2008)
Lin, Kao-Chao
;
Chen, Hsia-Wei
;
Juan, Chuan-Ping
;
Lai, Rui-Ling
;
Hsu, Yu-Ying
Field-emission devices with a novel self-focusing gate structure using carbon nanotubes as emitters have been fabricated. Without additional focusing electrodes, the self-focusing gate structure employed a pair of gate electrodes parallel with the vicinity of emitters, which resulted in an asymmetric emission area as compared with the conventional gate structure. Therefore, electrons emitted from the emitters gave rise to an overlapping region on the anode plate so that a reduction of spot size had been achieved. According to the simulation results and luminescent images, this self-focusing gate structure had good control of the trajectory of electrons and therefore showed a smaller luminescent spot size than the conventional one. This gate structure, which utilizes a simple fabrication process, has the advantages of low-cost manufacturing and large-area scalability, and therefore is promising for application in field emission displays. (c) 2008 The Electrochemical Society.
Characteristics of low-temperature pulse-laser-deposited (Pb,Sr)TiO3 films in metal/ferroelectric/silicon structure
(2007-01-07)
Wang, Jyh-Liang
;
Lai, Yi-Sheng
;
Lee, Trent Gwo-Yann
;
Chiou, Bi-Shiou
;
Tsai, Chun-Chien
In this study, pulsed- laser deposited ( Pb, Sr) TiO3 ( PSrT) films on p- type Si were studied at low substrate temperatures ranging from 300 to 450 degrees C for metal/ ferroelectric/ semiconductor applications. The substrate temperature strongly enhances film crystallinity without significant inter- diffusion at the PSrT/ Si interface and affects the electrical properties. As the substrate temperature increases, the films have smaller leakage currents, fewer trap states at the electrode interfaces, clockwise capacitance versus applied field hysteresis loops and larger memory windows correlated with superior crystallinity. Conversely, 300 degrees C- deposited films exhibit a small and counterclockwise loop with a positive shift of the flatband voltage, attributed to more negative trap charges within the films. However, the high substrate temperature ( 450 degrees C) may produce serious Pb - O volatilization, incurring more defects and leakage degradation. The analyses of fixed charge density and flatband voltage shift reveal the trap status and agree well with the leakage characteristic. An electron band model of the Pt/ PSrT/ Si electronic structure is proposed to explain the electrical behaviour. The excellent fatigue endurance with a small variation of memory windows (< 11%) after 1010 switching is also demonstrated.
Coaxial-Structured Solar Cells with Silicon Nanostructures
(2012)
Li, Hung-Hsien
;
Chen, Kuan-Heng
;
Chiou, Si-Ming
;
Liu, Han-Wen
;
Juan, Chuan-Ping
Coaxial-structured solar cells with different lengths silicon nanowires (SiNWs) fabricated by e-beam lithography and transformer coupled plasma reactive ion etching (TCP-RIE) were demonstrated in this paper. With the intrinsic amorphous silicon thickness of 15 nm and n-layer thickness of 25 nm, the short-current density and the conversion efficiency of the flat film solar cell were 17.58 mA/cm(2) and 3.16 %, respectively. Furthermore, the short-current density increased from 20.75 to 27.90 mA/cm(2) and the conversion efficiency increased from 3.59 to 4.69 % when the silicon nanowires length was increased from 0.5 to 1 mu m. The proposed coaxial-structured solar cells with SiNWs exhibited nearly 48.42 % efficiency enhancement over the plat film solar cell.