Browsing by Author "Cheng, JY"

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A novel planarization of oxide-filled shallow-trench isolation
(1997-01-01)
Cheng, JY
;
Lei, TF
;
Chao, TS
;
Yen, DLW
;
Lin, CJ
Two planarization approaches of the oxide-filled trench isolation have been evaluated. Results show that the oxide-filled shallow-trench isolation technology based on a chemical-mechanical polishing (CMP) process is difficult to control and has a poor uniformity. It also results in a dishing effect in wide field regions. On the other hand, a new planarization process can achieve an excellent uniformity and fully planar surface by using a combination of a masking polysilicon layer based on a CMP process, selective wet etching for oxide refill on active regions, short-time CMP process for oxide refill, and reactive ion etching etchback. Results also show that the high breakdown yield of the gate oxide and the low leakage current of the n(+)/p junction diodes with the novel planarization process demonstrates extremely low defect density from this process. This new process is a very promising candidate for oxide-filled shallow-trench isolation.
A novel shallow trench isolation technique
(1997-03-01)
Cheng, JY
;
Lei, TF
;
Chao, TS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Shallow-trench isolation processes which involve refilling using deposition of oxide and polysilicon were investigated. Our results show that the oxide-filled shallow-trench isolation technology based on chemical-mechanical polishing (CMP) is difficult to control and results in poor uniformity. Use of this technology also involves in the dishing effect in wide field regions. However, shallow-trench isolation technology using a masking nitride layer, polysilicon refill, the CMP process with high etch selectivity, and local oxidation of polysilicon is easily implemented and absolutely field oxide encroachment (bird's beak) free. Although the CMP process results in the dishing effect in wide field regions, the local oxidation of polysilicon can reduce the amount of dishing. The polysilicon-filled shallow-trench isolation process can also achieve excellent uniformity across 6-inch diameter silicon wafers due to the high etching selectivity of polysilicon to chemical-vapor-deposited (CVD) oxide and SiN. Moreover, the n(+)/p junction leakage current of polysilicon-filled shallow trenches is comparable to that of oxide-filled shallow trenches. This simple and easily controllable process is a very promising candidate for shallow trench isolation.
Characterization of polysilicon oxides thermally grown and deposited on the polished polysilicon films
(1998-04-01)
Lei, TF
;
Cheng, JY
;
Shiau, SY
;
Chao, TS
;
Lai, CS
This work examines the characteristics of polyoxides thermally grown and deposited an polished polysilicon films. A well-controlled chemical mechanical polishing (CMP) process is also presented to achieve a planar surface morphology Tot polysilicon films. The thermally-grown and deposited polyoxides on the polished polysilicon films exhibit a lower leakage current, higher dielectric breakdown field, higher electron barrier height, lower electron trapping, rate, lower density of trapped charges, and markedly higher charge to breakdown (Q(bd)) than the conventional polyoxide. In particular, the deposited polyoxide on the polished polysilicon film has the highest dielectric breakdown field, lowest electron trapping rate, and highest charge to breakdown due to the planar polyoxide/polysilicon interface. In addition, experimental results indicate that the trapped charges of the polished samples are located in the polyoxides' upper portion, which differs from conventional polyoxides. Undoubtedly, the deposited polyoxide on the polished polysilicon film considered herein is the most promising candidate to yield optimum characteristics of polyoxide.
Fabrication of thin film transistors by chemical mechanical polished polycrystalline silicon films
(1996-03-01)
Chang, CY
;
Lin, HY
;
Lei, TF
;
Cheng, JY
;
Chen, LP
A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP), In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm(2)/V-s, ON/OFF current ratio of 1.110(7), and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFT's.
Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors
(1996-11-01)
Lin, HY
;
Chang, CY
;
Lei, TF
;
Liu, FM
;
Yang, WL
A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.
Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors
(1996-11-01)
Lin, HY
;
Chang, CY
;
Lei, TF
;
Liu, FM
;
Yang, WL
A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.