Browsing by Author "Cheng, Jung-Chien"

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Effect of Ion-Implantation Temperature on Contact Resistance of Metal/n-Type 4H-SiC With Ar Plasma Treatment
(2019-03-01)
Tsui, Bing-Yue
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Cheng, Jung-Chien
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
It has been reported that Ar plasma treatment on the n-type 4H-SiC surface before metal deposition can reduce the contact resistance. In that work, the n(+) layer was formed by ion implantation at room temperature (RT). In this paper, it is found that Ar plasma treatment on the high-temperature (HT) implanted n+ layer degrades but not improves the contact resistance. A composition of RT/low-energy and HT/high-energy ion implantation can achieve low sheet resistance of the n+ layer and low contact resistance simultaneously. A twofold mechanism is proposed that the amorphous interfacial layer produced by Ar plasma treatment reduces the Schottky barrier height and the defects generated by RT ion implantation enhance current conduction by trap-assisted tunneling.
Effects of Rapid Thermal Annealing on Ar Inductively Coupled Plasma-Treated n-Type 4H-SiC Schottky and Ohmic Contacts
(2018-09-01)
Cheng, Jung-Chien
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Tsui, Bing-Yue
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effects of Ar inductively coupled plasma (ICP) treatment followed by a 600 degrees C-1000 degrees C rapid thermal annealing (RTA) on the n-type 4H-silicon carbide (SiC) Schottky-barrier diodes and n(+)-implanted ohmic contacts were investigated. The ICP treatment created a 3-nm-thick, sp(2)-C-rich, and amorphous layer at the SiC surface. The RTA repaired the bombardment-induced damages before metal deposition to avoid current degradation. This ICP + RTA-treated surface strongly pinned the Schottky- barrier height (SBH) at a minimum of 0.88 eV. In theory, the low SBH is beneficial to decrease the specific contact resistance (rho(C)). rho(C) of the ICP + RTA-treated Ti ohmic contacts decreased to lower than 10(-5) Omega.cm(2) after 400 degrees C post-metal deposition annealing (PMDA). However, the additional O atoms, fixed in the amorphous layer by RTA, affected the rho(C) reduction. Fortunately, due to the chemical affinity for O of Ti, the in-diffused Ti could contend for the O atoms against the Si-O bonds during the PMDA. Therefore, the oxidized barricade was decomposed gradually, leading to the lowest rho(C), 1.3 x 10(-6) Omega.cm(2), after 600 degrees C PMDA. The lowest rho(C) is 25x and 8x lower than that of the Ni silicide and the nontreated Ti contacts, respectively, at the same doping concentration.
Failure Analysis on TiAl Metallization Process for Ohmic Contact on 4H-SiC pMOSFET
(2019-01-01)
Hung, Chia-Lung
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Cheng, Jung-Chien
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Tsui, Bing-Yue
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
SiC is suitable for high-power and high-temperature applications due to its' wide energy bandgap and high thermal conductivity. Most literature focus on SiC nMOSFET due to higher electron mobility than hole. In this work, we fabricated 4H-SiC pMOSFET using TiAl alloy as contact metal to reduce the contact resistivity. However, ultrahigh leakage current was measured among all terminals of the pMOSFET. By comparing with different contact schemes, the failure mechanism is attributed to Al spiking into the underneath poly-Si and SiO2 during the metallization process. Using suitable blocking layer such as LPCVD Si3N4 (300 nm) or PECVD Si3N4 (100 nm) on SiO2 (200 nm) can avoid Al spiking so that conventional pattern topology and TiAl metallization process can be used on device fabrication.
Multi-gate non-volatile memories with nanowires as charge storage material
(2010-05-01)
Tsui, Bing-Yue
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Wang, Pei-Yu
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Chen, Ting-Yeh
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Cheng, Jung-Chien
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電子工程學系及電子研究所
Multi-gate non-volatile memory (NVM) cell is a promising approach in the next generation. In this work, the performance of NVMs using nanocrystals (NCs) and nanowires (NWs) as charge trapping materials were evaluated by three-dimensional simulation. It is found that the NWs located at different positions have different charge injection speeds. And the NW density will strongly affect the charge injection efficiency. The NW at channel center can result in large memory window and acceptable channel controllability. Although the total charges injected into NWs is lower than that injected into NCs under the same programming condition, using NWs as charge trapping material exhibits larger memory window and better channel controllability. It is suggested that the NW is a better choice than NC to be charge storage material from the perspective of memory performance. (C) 2010 Elsevier Ltd. All rights reserved.
Reduction of Specific Contact Resistance on n-Type Implanted 4H-SiC Through Argon Inductively Coupled Plasma Treatment and Post-Metal Deposition Annealing
(2017-12-01)
Cheng, Jung-Chien
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Tsui, Bing-Yue
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effects of Ar inductively coupled plasma (ICP) treatment on the Ohmic contact on n(+)-implanted SiC were investigated in this letter. The effects of ICP treatment were negligible on the Ni-silicide contact, because the treated surface layer was consumed during silicide formation. However, for the Ti contact, as the annealing temperature increased, the ion-bombardment-induced damage layer transformed to a uniform amorphous C-rich layer, and the specific contact resistance of the ICP-treated Ti contact decreased to 8.3 x 10(-7) Omega-cm(2) after 600 degrees C annealing. This is the lowest value achieved at such a low process temperature. Thus, appropriate ICP treatment and annealing can be used to form low-resistivity Ohmic contacts with a lower thermal budget that are comparable with Ni-based silicide Ohmic contacts.
Schottky barrier height modification of metal/4H-SiC contact using ultrathin TiO2 insertion method
(2014-04-01)
Tsui, Bing-Yue
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Cheng, Jung-Chien
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Lee, Lurng-Shehng
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Lee, Chwan-Ying
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Tsai, Ming-Jinn
The fabrication processes, electrical characteristics, and reliability of the Schottky barrier diodes (SBDs) on an n-type 4H-silicon carbide (SiC) substrate are investigated. To modulate the Schottky barrier height (SBH), titanium dioxide (TiO2) is inserted at the interface between the metal and the SiC substrate. Ni, Mo, Ti, and Al are chosen to form SBDs. The maximum SBH modulation of 0.3 eV is obtained with a 5-nm-thick TiO2 layer. The SBH pinning factors of the SBDs without TiO2 insertion and with 2-nm-thick TiO2 insertion are similar. Therefore, the mechanism of the SBH modulation is attributed to the interface dipole-induced potential drop. Finally, the reliability of the SBD with TiO2 insertion is evaluated. The SBH, ideality factor, and reverse leakage current are stable after high forward current stress at 300A/cm(2) for 15000 s. This work provides a simple method to modulate the SBH on SiC and is feasible for SBD application. (C) 2014 The Japan Society of Applied Physics
Strong Fermi-level pinning induced by argon inductively coupled plasma treatment and post-metal deposition annealing on 4H-SiC
(2017-07-01)
Tsui, Bing-Yue
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Cheng, Jung-Chien
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Yen, Cheng-Tyng
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Lee, Chawn-Ying
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電機學院
The effect of pre-metal deposition cleaning on 4H-SiC Schottky barrier diodes (SBDs) by using Ar ion bombardment in an inductively coupled plasma (ICP) chamber was investigated. The ICP treatment produced a thin and Si-depleted amorphous layer on the SiC surface. Partial graphitization was observed in the amorphous layer after post-metal deposition (PMD) annealing. This interfacial layer strongly pinned the Schottky barrier height (SBH). PMD annealing at 500 degrees C resulted in a constant SBH (approximately 1.1 eV) and narrow SBH distribution (standard deviation < 3 meV). However, the amorphous layer was consumed after 600 degrees C PMD annealing due to interfacial reactions. These results suggest that the Ar ion bombardment technique with a suitable thermal budget can be used to form relatively uniform SBDs. (C) 2017 Elsevier Ltd. All rights reserved.