Browsing by Author "Cheng, KH"

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A concurrent 0.18-mu m CMOS self-biased dual-band driver amplifier for IEEE 802.11 a/b/g
(2004)
Jou, CF
;
Cheng, KH
;
Chen, JL
;
傳播研究所
;
Institute of Communication Studies
A 2.4 GHz / 5.2 GHz self-biased dual band CMOS driver amplifier with a 9.8-dBm output power using TSMC 0.18-mu m IP6M standard CMOS process is described. The CMOS amplifier designed on Rogers R04003 printed-circuit-board (PCB) with a single input and a single output signal chain is simultaneously optimized for wireless local area network (WLAN) 2.4 GHz / 5.2 GHz applications. Simulation results show that the driver amplifier exhibits an Output power about 9.7-dBm in both 2.4 GHz and 5.2 GHz, output interception point (OIP3) of 24dBm with power added efficiency (PAE) = 27% and PAE =24% in 2.4GHz and 5.2 GHz, respectively. The die size is 0.85x0.7 mm(2).
A low power, fast-switching frequency synthesizer of 5.2GHz WLANs
(2004)
Cheng, KH
;
Chen, CH
;
Jou, CF
;
電信工程研究所
;
Institute of Communications Engineering
A 1.5V supply, low power consumption and fast switching integer-N frequency synthesizer is presented. The synthesizer consists of LC-tank VCO with quadrature output, D-type flip-flop (DFF) prescalar, swallow-counter, phase-frequency detector, charge pump and 4(th) order loop filter. A noble design procedure for loop filter is also presented with the aid of MATLAB program. The phase noise of VCO is -106dBc/Hz @1MHz offset. Total power consumption of synthesizer is 20.5mW. Settling time is 40us. The synthesizer is fabricated by TSMC 0.25um CMOS technology, and is suitable for HiperLAN II and IEEE 802.11a lower side-band applications.
An ultra low power 2.4GHz CMOS VCO
(2003)
Jou, CF
;
Cheng, KH
;
Hsieh, HC
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傳播研究所
;
Institute of Communication Studies
A low power voltage-controlled oscillator (VCO) for IEEE 802.11b direct conversion receiver is demonstrated. The VCO is fabricated by TSMC 0.25-mum; based on the measurement results, the tuning range is 187MHz (7.78%); phase noise is -73.62dBc/Hz@600kHz offset and -82.44dBc/Hz@1MHz offset at 2.4GHz. The circuit draws only 53 muA current for the VCO core from a 1.5V supply.
AuBe Ohmic contacts to p-type ZnTe
(1998-12-10)
Lan, WH
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Lin, WJ
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Cheng, YC
;
Tai, K
;
Tasi, CM
Ohmic contacts of AuBe to p-ZnTe show a minimum specific contact resistance of 3.0 x 10(-6) Ohm cm(2) for a p-doping level of 1.6 x 10(19) cm(-3) and at an annealing temperature of 200 degrees C. The beryllium is very effective at improving the electrical properties of p-type contacts to ZnTe.
Design of a 0.25-mu m CMOS 5.25GHz transceiver front-end
(2003)
Jou, CF
;
Huang, PR
;
Cheng, KH
;
電信工程研究所
;
Institute of Communications Engineering
This paper describes the design consideration and simulation performance for a fully integrated CMOS RF front-end for 5.25 GHz application. The single chip front-end circuit consists: a 2.65dB insertion loss transmit/receive switch (T/R switch), a 13dB power gain, 2.9dB NF low noise amplifier (LNA), and a 15dBm Pout-1dB power amplifier (PA). The IC has fabricated in a TSMC 0.25-mum CMOS technology. To achieve single chip design target, this chip was designed without any off-chip matching component. The front-end circuit was designed for two operation modes: transmission mode (TX) and receiving mode (RX). We can switch two operation modes by changing the control voltage of the T/R switch. The simulation results of the TX mode has the power gain 7.27 dB and the Pout-1dB is 12 dBm. The RX mode power gain is 9.64 dB and the IIP3 is 1.1 dBm.
Design of a concurrent dual-band receiver front-end in 0.18um CMOS for WLANs IEEE 802.11a/b/g applications
(2004)
Jou, CF
;
Cheng, KH
;
Lien, WC
;
Wu, CH
;
Yen, CH
A fully monolithic dual-band concurrent receiver chip for IEEE 802.11 a, 802.11 b and 802.11 g applications is presented in a 0.18-mum CMOS 1P6M technology. A low IF architecture was chosen in order to achieve a low-cost and low-power solution with a high level of integration compared to direct conversion architecture. This mixer can operate as a sub-harmonic mixer and even as a traditional Gilbert mixer if LO ports connecting to each other to found two RF inputs and two LO inputs. For a 1.8V power supply, the overall power consumptions are 84.3 mW, with 3.5 dB and 6.3 dB overall receive-chain noise figure for 2.45 GHz and 5.25 GHz, respectively.
Design of a fully integrated high linearity dual-band CMOS LNA
(2003)
Jou, CF
;
Cheng, KH
;
Huang, PR
;
Chen, MC
;
電信工程研究所
A fully-integrated dual-band LNA (Low Noise Amplifier) with high linearity is presented in this thesis. Designed and implemented in 0.25 mu m mixed-signal CMOS process, the LNA simultaneously delivered narrow-bans gain and matching at 2.45GHz and 5.25GHz. The LNA exhibits input matching with S-11 of -20.48dB at 2.45GHz and -16.6dB at 5.25GHz. And it achieves small-signal gain of 5.78dB and 3.24dB, noise figure 4.7dB and 5.69dB, and IIP3 7dBm and 17dBm.
Dual band CMOS power amplifier for WLAN applications
(2003)
Jou, CF
;
Cheng, KH
;
Lin, CM
;
Chen, JL
;
傳播研究所
A 2.4 GHz / 5.2 GHz dual band CMOS power amplifier (PA) with a 21-dBm output power using 0.25 - mu m 1P5M standard CMOs process is described. In this paper, we present a CMOs PA with a single input and a single output signal chain which simultaneously optimized for wireless local area network (WLAN) 2.4 GHz / 5.2 GHz applications designed on Rogers RO4003 printed-circuit-board (PCB). The simulated dual-band PA biased at Class-A exhibiting P-1dB = 21dBm in both 2.4 GHz and 5.2 GHz with power added efficiency (PAE) = 26% and PAE = 18% separately. The performances of the designed PA presents the standard CMOs process has the potential for the PAs of 2.4 GHz / 5.2 GHz WLAN applications.