Browsing by Author "Cheng, Kuo-Hsing"

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A Micro-Network on Chip with 10-Gb/s Transmission Link
(2009)
Liu, Wei-Chang
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Lin, Chih-Hsien
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Jou, Shyh-Jye
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Lu, Hung-Wen
;
Su, Chau-Chin
In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13 mu m CMOS technology. The core area of this chip is 990 mu m*1600 mu m and the power consumption is 155mW (60mW for micro-switches and 95mW for 10-Gb/s data transceiver) at 1.2V supply voltage with 10-Gb/s transmission data rate.
All Digital Phase-Locked Loop Using Active Inductor Oscillator and Novel Locking Algorithm
(2011)
Huang, Tzu-Chi
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Huang, Hong-Yi
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Liu, Jen-Chieh
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Cheng, Kuo-Hsing
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Luo, Ching-Hsing
A fast locking all-digital phase-locked loop (ADPLL) with the active inductor oscillator is proposed. An LC-tank DCO with a tunable active inductor can obtain a wider operational frequency range, smaller area and higher signal quality. The proposed frequency and phase locking algorithm can achieve good jitter performance, high frequency accuracy, and low circuit complexity. The ADPLL is designed using a 0.18 um CMOS process. The operational frequency range of the ADPLL is from 318 MHz to 458 MHz. The RMS and the peak-to-peak jitters at 402 MHz are 4.2 ps and 94 ps, respectively. The core size is 390x390 um(2). The power consumption is 5.4 mW at 416 MHz.
Gm-C Filter with Automatic Calibration Scheme
(2016)
Huang, Hong-Yi
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Chen, Kun-Yuan
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Xie, Jia-Hao
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Lee, Ming-Ta
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Hong, Hao-Chiao
This work presents a fifth-order OTA-C band-pass filter applying Elliptic low-pass filter and complex filter techniques. The frequency error of the filter due to the effect of process variations is induced by integrating the passive components with the operational transconductance amplifier on chip. A filter circuit with automatic calibration scheme can make the frequency less dependent on process, voltage, and temperature variations. The layout of a test chip is realized using a 0.18 um 1P6M CMOS process. Post-layout simulation demonstrates that the center frequency of the band pass filter is 450 kHz and the dynamic range is 35 dB, It has a total power consumption of 0.14mW.
Low-Voltage Indoor Energy Harvesting Using Photovoltaic Cell
(2016)
Huang, Hong-Yi
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Yen, Shao-Zu
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Chen, Jhen-Hong
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Hong, Hao-Chiao
;
Cheng, Kuo-Hsing
This work presents a low-voltage indoor energy harvesting using photovoltaic cell. The system doesn\'t use a dc-dc converter to boost the output voltage so that large external inductors and large capacitors are eliminated. A rechargeable battery is connected to the output for storing the energy. No other external components are needed in the system. A test chip is implemented using a 0.18um CMOS process with a chip area of 0.85x0.85mm(2) and a power consumption of 272uW. This solar cell provides a voltage of 0.4V similar to 0.55V to the test chip at a minimum illumination of 61 similar to 625 Lux. A maximum efficiency of 54% can be obtained when the supply voltage is 0.5V.