Browsing by Author "Cheng, L. W."

Now showing 1 - 3 of 3

Reliability of ALD Hf-based high K gate stacks with optimized interfacial layer and pocket implant engineering
(2007)
Mao, A. Y.
;
Lin, W. M.
;
Yang, Cw.
;
Hsieh, Y. S.
;
Cheng, L. W.
Reliability of ALD (Atomic Layer Deposition) HfSiON high K gate stacks is greatly enhanced with a property engineered IL (Interfacial Layer) between the gate dielectrics and the Si substrate. We report that the HfSiON, while deposited on an optimized plasma-based IL containing [N], exhibits strong resistance to the bombardment from heavy pocket implant species, achieving significantly reduced leakage and excellent reliability characteristics, compared to the HfSiON without an optimized IL and to the silicon oxynitride control wafers.
The Observation of Trapping and Detrapping Effects in High-k Gate Dielectric MOSFETs by a New Gate Current Random Telegraph Noise (I(G)-RTN) Approach
(2008)
Chang, C. M.
;
Chung, Steve S.
;
Hsieh, Y. S.
;
Cheng, L. W.
;
Tsai, C. T.
A new method, called gate current Random Telegraph Noise (I(G) RTN), was developed to analyze the oxide quality and reliability of high-k gate dielectric MOSFETs. First, a single electron trapping/detrapping from process induced trap in nMOSFET was observed and the associated physical mechanism was proposed. Secondly, I(G) RTN has also been successfully applied to differentiate the difference in electron tunneling mechanism for a device under high-field or low-field stress. Finally, the soft-breakdown (SBD) behavior of a device can be clearly identified. Its I(G) RTN characteristic is different from that before soft-breakdown. It was found that SBD will indeed induce extra leakage current as a result of an additional breakdown path.
Twin-GD: A new twin gated-diode measurement for the interface characterization of ultra-thin gate oxide MOSFET's with EOT down to 1nm
(2006)
Lee, G. D.
;
Chung, S. S.
;
Mao, A. Y.
;
Lin, W. M.
;
Yang, C. W.
In this paper, a new twin gated-diode (T-GD) method has been greatly improved for the oxide interface characterization of MOS devices with gate oxide as thin as 1nm (EOT). With the scaling of gate oxide thickness into 1mn regime, reported GD measurement can not give correct measurement due to gate tunneling leakage current. Here, we provide a simple method to remove this limitation. This method has been demonstrated successfully for the ultra-thin (EOT = 10.2 angstrom) gate oxide nMOSFET devices. Application of the method to the PBTI effects of high-k gate dielectric devices has been demonstrated. It was found that high-K device has worse gate oxide quality, but its interface damage is less than that of control oxide.