Browsing by Author "Cheng, Liang-Chia"

Now showing 1 - 8 of 8

A 0.48V 0.57nJ/Pixel Video-Recording SoC in 65nm CMOS
(2013-01-01)
Lin, Tay-Jyi
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Chien, Cheng-An
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Chang, Pei-Yao
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Chen, Ching-Wen
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Wang, Po-Hao
A Robust Incremental Power Grid Analyzer by Macromodeling Approach and Orthogonal Matching Pursuit
(2012)
Lee, Yi-Hsuan
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Lee, Yu-Min
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Cheng, Liang-Chia
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Chang, Yen-Tang
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交大名義發表
As VLSI techniques are getting more and more advanced, the size of the power grid network increases dramatically. Therefore, the power grid analysis becomes a challenging task during the design procedure. This work utilizes the macromodeling technique [1] and enhances the Orthogonal Matching Pursuit (OMP) based method [2] to develop an effective and robust incremental analysis method for the power grid network, MA-OMPt. Given a power grid network, MA-OMPt not only can deal with the change of its element values but also can handle the modification of its topology. The experimental results show that MA-OMPt can be an order of magnitude faster than the OMP-based method [2] which can only deal with the change of element values of the power grid. The experimental results also demonstrate that MA-OMpt can accurately and efficiently handle the modified topology of the power grid network.
A System-Level Thermal Simulator with Automatic Meshing Techniques
(2018-01-01)
Wang, Jui-Hung
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Lee, Yu-Min
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Hsiao, Hsuan-Hsuan
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Cheng, Liang-Chia
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電機工程學系
The grid structure of most numerical thermal simulators has to be designed artificially. Designers might need to try many different grid structures for getting accurate thermal profiles, and, hence, waste a great of runtime. In order to solve this problem, this work presents a system-level thermal simulator, DeNAFE, which can adaptively mesh thermal grids automatically. First, we develop and employ a fast thermal estimation engine to roughly obtain the thermal profile of the system. Then, with this thermal profile, we propose and utilize an adaptive meshing procedure to decide its grid structure and perform thermal simulation. Compared with a commercial tool, ANSYS Icepak, the experimental results show that the speedup of DeNAFE can be up to two orders of magnitude with only 6: 09% maximum error for all chips in the steady-state thermal simulation. Furthermore, the error of chips is less than 5: 25%, the error of screen/skin is less than 6: 03%, and the speedup can be over 171: 12 times in the transient simulation.
Learning Based Mesh Generation for Thermal Simulation in Handheld Devices with Variable Power Consumption
(2019-01-01)
Lo, Wen-Sheng
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Chiou, Hong-Wen
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Hsu, Shih-Chieh
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Lee, Yu-Min
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Cheng, Liang-Chia
This work utilizes machine learning techniques to achieve learning based mesh generation for the thermal simulator. In the learning stage, first, we generate many power value sets of application processors and apply the superposition technique to obtain the temperature raw data of material blocks. We, then, use these thermal data and several defined thermal gradient ranges to obtain different appropriate mesh-size sets of material blocks for each power value set. We construct the regressions that are capable of predicting targets as a supervised learning task, and the architecture of regression model includes seven hidden layers. After the learning stage, we integrate the learning based mesh decision engine into a developed system-level thermal simulator, which is built by the finite difference method. The experimental results show that the temperature profiles of the handheld device calculated by the developed thermal simulator with learning based mesh generation fits the results obtained by a commercial tool pretty well with less runtime usages. Moreover, the learning based mesh decision engine is much more efficient than the artificial mesh decision.
Power Delivery Network Design for Wiring and TSV Resource Minimization in TSV-Based 3-D ICs
(2013-01-01)
Wei, Shu-Han
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Lee, Yu-Min
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Ho, Chia-Tung
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Sun, Chih-Ting
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Cheng, Liang-Chia
This work presents effective techniques for minimizing wiring resources and power TSVs (PTSVs) of 3-D power delivery network design under IR drop constraints. First, a 3-D power grid topology optimization is performed to generate power grid by utilizing locally uniform and globally non-uniform power grid configurations. After that, two developed power TSV planners are executed to minimize the maximum IR drop without the full-chip power-grid analysis. Finally, the above procedures are repeatedly performed with a rescue procedure to remedy the violated constraints until the designed PDN is satisfied. To further enhance the design procedure, a partition-based design flow is proposed by dividing the entire chip into tiles, and each of them is designed independently by the proposed procedure. The experimental results demonstrate the effectiveness of the developed methodology and indicate that the consideration of partition-based strategy in the design flow is imperative.
Power Delivery Network Design for Wiring and TSV Resource Minimization in TSV-Based 3-D ICs
(2013)
Wei, Shu-Han
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Lee, Yu-Min
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Ho, Chia-Tung
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Sun, Chih-Ting
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Cheng, Liang-Chia
This work presents effective techniques for minimizing wiring resources and power TSVs (PTSVs) of 3-D power delivery network design under IR drop constraints. First, a 3-D power grid topology optimization is performed to generate power grid by utilizing locally uniform and globally non-uniform power grid configurations. After that, two developed power TSV planners are executed to minimize the maximum IR drop without the full-chip power-grid analysis. Finally, the above procedures are repeatedly performed with a rescue procedure to remedy the violated constraints until the designed PDN is satisfied. To further enhance the design procedure, a partition-based design flow is proposed by dividing the entire chip into tiles, and each of them is designed independently by the proposed procedure. The experimental results demonstrate the effectiveness of the developed methodology and indicate that the consideration of partition-based strategy in the design flow is imperative.
Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells
(2014-12-01)
Luo, Shien-Chun
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Chang, Kuo-Chiang
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Chen, Ming-Pin
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Huang, Ching-Ji
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Chiu, Yi-Fang
This brief presents an implementation of ultralow-power microcontrollers that use a separate clock network voltage (SCNV) to correct unexpected errors produced by on-chip variations (OCVs). Separating the clock network voltage requires amendments in the standard cell library and physical designs. Here, the experiments used a 65-nm technology that exhibited considerable OCVs, which caused write and retention errors in clocked storage cells and limited the voltage scaling of microcontrollers. Using the SCNV provides an extraordinary operability to correct errors in the low-voltage clocked storage cells. In addition, the area overhead of the proposed implementation is negligible. Applying the SCNV, the measurement results indicate that the microcontrollers can be operated below 0.3 V, over 0.15-V extension in voltage scaling, and achieve the optimal energy consumption at 0.34 V. Separating the clock network voltage has tradeoff issues in system timing and energy consumption based on the measurement results, and this brief discusses proper applications.
Thermal Modeling and Design on Smartphones with Heat Pipe Cooling Technique
(2017-01-01)
Chiou, Hong-Wen
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Lee, Yu-Min
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Hsiao, Hsuan-Hsuan
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Cheng, Liang-Chia
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電信工程研究所
While the performance of smartphones becomes much higher, the application processor consumes considerable power. Thus, it is hard to meet thermal constraints by using conventional cooling techniques. Fortunately, since heat pipes can efficiently transfer the thermal energy from hot regions to cool regions, temperatures in hot regions can be reduced greatly. Hence, in the past three years, the heat pipe cooling techniques have been applied to smartphones by industries. However, although the time-consuming commercial simulation tools, such as ANSYS Fluent, can provide accurate thermal maps, they may lead to inefficiency during design stages. Besides, the compact thermal model for bended heat pipes is still underdeveloped. Therefore, efficient thermal simulation for smartphones with bended heat pipes should be developed for the design stage. Furthermore, the routing of bended heat pipe should be optimized to obtain more thermal energy transfer. This work presents a compact thermal model for bended heat pipes and an efficient thermal simulator for smartphones. Moreover, with inconsistent maze routing and dynamic thermal weight assignment, a thermal-driven routing algorithm is proposed for optimizing the design of bended heat pipe. Compared with ANSYS Fluent, the thermal simulation with bended heat pipe thermal model can achieve at least three orders of magnitude speedup with only 3.58% maximum error for all chips. The proposed heat pipe routing algorithm can reduce at least 10.86% of the maximum temperatures for application processors.