Browsing by Author "Cheng, Long"

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Drag force of Anisotropic plasma at finite U(1) chemical potential
(2016-05-05)
Cheng, Long
;
Ge, Xian-Hui
;
Wu, Shang-Yu
;
電子物理學系
;
Department of Electrophysics
We perform the calculation of the drag force acting on amassive quark moving through an anisotropic N = 4 SU(N) Super Yang-Mills plasma in the presence of a U(1) chemical potential. We present the numerical results for any value of the anisotropy and arbitrary direction of the quark velocity with respect to the direction of the anisotropy. We find the effect of the chemical potential or charge density will enhance the drag force for our charged solution.
Efficient Implementation of Boolean and Full-Adder Functions With 1T1R RRAMs for Beyond Von Neumann In-Memory Computing
(2018-10-01)
Wang, Zhuo-Rui
;
Li, Yi
;
Su, Yu-Ting
;
Zhou, Ya-Xiong
;
Cheng, Long
In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 10(7) cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture.
In-Memory Digital Comparator Based on a Single Multivalued One-Transistor-One-Resistor Memristor
(2020-03-01)
Cheng, Long
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Zheng, Hao-Xuan
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Li, Yi
;
Chang, Ting-Chang
;
Sze, Simon M.
In-memory computing based on multivalued memristive device opens the vision of building computing system with less resource and high performance. In this article, we achieved three distinguishable resistance states in mature one-transistor-one-resistor (1T1R) memristor. Furthermore, based on a single multivalued 1T1R device, for the first time, we successfully demonstrated an area-efficient in-memory digital comparator, which will cost five logic gates in complementary metal oxide semiconductor (CMOS) approach. The method is also easily expanded to multibit. Our work could be a representative of using multivalued nonvolatile memory device in digital information processing with improved performance.
Reconfigurable Boolean Logic in Memristive Crossbar: The Principle and Implementation
(2019-02-01)
Hu, Si-Yu
;
Li, Yi
;
Cheng, Long
;
Wang, Zhuo-Rui
;
Chang, Ting-Chang
In-memory computing based on memristive logic is considered as a prospective non von Neumann computing paradigm. In this letter, we systematically analyze the four-variable logic method and map it into the operation of two anti-serial complementary memristors in the crossbar array architecture. Arbitrary Boolean logic can be implemented within three cycles with the experimental evidence of reconfigurable NAND, NOR, and XOR logic using Pt/HfO2/TiN devices. Taking advantage of the functional flexibility, a parallel 1-bit full adder that can be realized in 8 cycles within a 4 x 3 array has been designed and verified in simulation.