Browsing by Author "Cheng, Osbert"

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A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash With Excellent Immunity to Sneak Path
(2017-12-01)
Hsieh, E. Ray
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Kuo, Yen Chen
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Cheng, Chih-Hung
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Kuo, Jing Ling
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Jiang, Meng-Ru
In this paper, we have demonstrated an oxygen-vacancy-based bipolar RRAM on a pure logic 14-nm-node HKMG FinFET platform. A unit cell of the memory consists of a control transistor (FinFET) and a storage transistor (a second FinFET). The later performs as a bipolar RRAM. This unit cell can be integrated in an AND-type memory array. The memory cell has an ON/OFF ratio equal to 200 and 400 for the n-type and p-type FinFET RRAMs, respectively, endurance larger than 400 and 1000 times for n- and p-type devices, respectively, and the retention test for over 1 month under 125 degrees C temperature environment. To analyze the array performance of the AND-type FinFET RRAM at the circuit level, we have further discussed the issues of the sneak path and disturbance, in which an active-fin isolation of FinFET in an AND-type array has been suggested to minimize the leakage current induced by sneak paths. The results have shown a large window with up to 103 ON/OFF ratio, 30% standby power reduction, and 90% active power reduction with reference to the conventional AND-type array. As a result, the bipolar FinFET RRAM exhibits great potential for the embedded memory applications, in particular it can be extended to 28-nm HKMG and the FinFET platform beyond 14-nm technology node, to fill the Moore's gap between the high-performance logic and the embedded memory.
A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 10(12) Endurance
(2019-01-01)
Hsieh, E. R.
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Chang, H. Y.
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Chung, Steve S.
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Chen, T. P.
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Huang, S. A.
In this work, we will explore pure logic FinFET devices to realize the functionality of linear weight tuning capability as electric synapses. The unit cell of this new FinFET synapse is composed of two identical FinFETs in series; one serves as control and the other one as storage. This new FinFET synapse exhibits ideal linearity with nearly infinity training cycles (>10(12)). much lower programming voltage, 0.85V, and faster speed, 2.5ns. It can also analogically increase or decrease the transistor's V-th, to vary the drain conductance. As far as the analog performance is concerned, it performs excellent linearity and a wide tuning-window (20x) of weight-tuning capability. 1kb synaptic array has also been designed. The spice-simulated results have shown that new FinFET synaptic array can expand the array-size to 64x64, exhibiting 300x of SNR, w.r.t. that of RRAM array. Finally, the training of the neural network based on the proposed FinFET synapse can achieve 97.43% accuracy as high as the GPU one does.
Abnormal interface state generation under positive bias stress in TiN/HfO2 p-channel metal-oxide-semiconductor field effect transistors
(2012-09-24)
Lo, Wen-Hung
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Chang, Ting-Chang
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Tsai, Jyun-Yu
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Dai, Chih-Hao
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Chen, Ching-En
This Letter studies positive bias stress-induced abnormal interface state on TiN/HfO2 p-channel metal-oxide-semiconductor field effect transistors. It can be found that the degradation is associated with electron trapping, resulting in V-th shift but without subthreshold slope degradation. However, charge pumping current (I-CP) shows a significant degradation after stress. Accordingly, the impact ionization-induced Nit located HfO2/SiO2 is proposed to demonstrate the ICP degradation. The AC stress with several frequencies is used to evidence the occurrence of impact ionization. Further, the device with additional pre-existing N-it located SiO2/Si has insignificant degradation due to reduction in stress electric field. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4752456]
Abnormal sub-threshold swing degradation under dynamic hot carrier stress in HfO2/TiN n-channel metal-oxide-semiconductor field-effect-transistors
(2013-07-08)
Tsai, Jyun-Yu
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Chang, Ting-Chang
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Lo, Wen-Hung
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Chen, Ching-En
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Ho, Szu-Han
This work finds abnormal sub-threshold swing (S.S.) degradation under dynamic hot carrier stress (HCS) in n-channel metal-oxide-semiconductor field-effect-transistors with high-k gate dielectric. Results indicate that there is no change in S.S. after dynamic HCS due to band-to-band hot hole injection at the drain side which acts to diminish the stress field. Moreover, the impaired stress field causes the interface states to mainly distribute in shallow states. This results in ON state current and transconductance decreases, whereas S.S. degradation is insignificant after dynamic HCS. The proposed model is confirmed by one-side charge pumping measurement and gate-to-drain capacitance at varying frequencies. (C) 2013 AIP Publishing LLC.
Abnormal temperature-dependent floating-body effect on Hot-Carrier Degradation in PDSOI n-MOSFETs
(2014-12-01)
Liu, Kuan-Ju
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Chang, Ting-Chang
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Yang, Ren-Ya
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Chen, Ching-En
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Ho, Szu-Han
This letter investigates abnormal degradation behavior after hot-carrier stress in partially-depleted silicon-oninsulator n-channel metal-oxide-semiconductor field effect transistors. It is found that the hot-carrier-induced degradation under floating body (FB) operation is more serious than that under grounded body (GB) operation due to the floating body effect (FBE). Furthermore, the degradation is independent on temperature under GB operation, because impact ionization is virtually independent on temperature under large VD. However, the degradation under FB operation becomes less serious with increasing temperature. This is due to a smaller source/body PN junction band offset at a high temperature, which causes fewer accumulated holes at the body terminal and reduces the FBE. (C) 2014 Elsevier B.V. All rights reserved.
Abnormal threshold voltage shift under hot carrier stress in Ti1-xNx/HfO2 p-channel metal-oxide-semiconductor field-effect transistors
(2013-09-28)
Tsai, Jyun-Yu
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Chang, Ting-Chang
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Lo, Wen-Hung
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Ho, Szu-Han
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Chen, Ching-En
This work investigates the channel hot carrier (CHC) effect in HfO2/Ti1-xNx p-channel metal oxide semiconductor field effect transistors (p-MOSFETs). Generally, the subthreshold swing (S. S.) should increase during CHC stress (CHCS), since interface states will be generated near the drain side under high electric field due to drain voltage (V-d). However, our experimental data indicate that S. S. has no evident change under CHCS, but threshold voltage (V-th) shifts positively. This result can be attributed to hot carrier injected into high-k dielectric near the drain side. Meanwhile, it is surprising that such V-th degradation is not observed in the saturation region during stress. Therefore, drain-induced-barrier-lowering (DIBL) as a result of CHC-induced electron trapping is proposed to explain the different V-th behaviors in the linear and saturation regions. Additionally, the influence of different nitrogen concentrations in HfO2/Ti1-xNx p-MOSFETs on CHCS is also investigated in this work. Since nitrogen diffuses to SiO2/Si interface induced pre-N-it occurring to degrades channel mobility during the annealing process, a device with more nitrogen shows slightly less impact ionization, leading to insignificant charge trapping-induced DIBL behavior. (C) 2013 AIP Publishing LLC.
Abnormal Transconductance Enhancement under Positive Bias Stress in Nanoscale n-Channel Fin Field-Effect-Transistors
(2016)
Liu, Kuan-Ju
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Chang, Ting-Chang
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Lin, Chien-Yu
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Chen, Ching-En
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Tsai, Jyun-Yu
This work demonstrates an abnormal transconductance (GM) enhancement after positive bias stress (PBS) in n-channel high-k/metal gate stacked fin-field-effect-transistors. This abnormal GM enhancement is observed only in short channel devices. With the speculation that hole-trapping-induced electron accumulation is the dominant mechanism, PBS with floating source and drain is adopted as an investigative approach. This, together with the electric field simulation, verifies that hole-trapping in the HfO2 and SiN near the gate corner induces electron accumulated at the ends of the channel length. Such a phenomenon results in a shortening of effective channel length and further GM enhancement. (C) 2016 The Electrochemical Society. All rights reserved.
An Energy Efficient FinFET-based Field Programmable Synapse Array (FPSA) Feasible for One-shot Learning on EDGE AI
(2018-01-01)
Kuo, J. L.
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Chen, H. W.
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Hsieh, E. R.
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Chung, Steve S.
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Chen, T. P.
A pure logic 14nm FinFET with capabilities of linearly tunable V-th and excellent retention has been implemented as synapses in neuromorphic system., a Field Programmable Synapse Array (FPSA) has been adopted to replace conventional R-based memory Synapse Array (RSA). Thanks to the wide range of V-t-tuning ability, 200X on/off ratio, and the ultra-small variability, 12%, results showed that the training power and SN ratio of FPSA are 10 times and 50 times smaller than those of the RSA, respectively. Two applications were demonstrated on FPSA array for one-shot learning applications. First, FPSA is used to detect handwritten digits of MNIST dataset. "Learned it by once" can be achieved in this task. Furthermore, FPSA has been applied to recognize goldfish in Cifar 100 dataset after learned the other 4 fish species. With the assistance from one-shot learning, results show the machine learned it faster and better on EDGE. This demonstrates the feasibility of FPSA for low-power and cost-effective synapse-based one-shot learning applications in the AIoT era.
An Experimental Approach to Characterizing the Channel Local Temperature Induced by Self-Heating Effect in FinFET
(2018-01-01)
Hsieh, E. Ray
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Jiang, Meng-Ru
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Lin, Jian-Li
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Chung, Steve S.
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Chen, Tse Pu
In this paper, we have developed a methodology of a lateral profiling technique of the channel local temperature in 14 nm FinFET, incurred by the self-heating effect (SHE). As SHE happens, the thermal source generated near the drain will dissipate toward the source side. Since the interaction between RTN trap and channel carriers is very sensitive to the temperature, the channel local temperature can be extracted through this interaction process between random-telegraph-noise (RTN) trap and carriers, and the position of the channel local temperature can be obtained from the RTN trap position. The results show that the highest temperature happens at the drain edge during SHE and pFinFET exhibits a much higher temperature than that of nFinFET. Furthermore, the distribution of channel local temperature can be described by the Fourier's law of thermal conduction. Averaged channel temperature can be used to extract the thermal resistance, R-th, which increases rapidly as the channel length is scaled down to 20 nm, further degrading the SHE, in terms of a significant short channel effect. We also found that the incremental channel resistance is proportional to the incremental channel local temperature, whose slope indicates the degree of SHE, and the slope of pFinFET is larger than that of nFinFET. Finally, SHE will cause 10% and 14% degradation of IdVds for n- and pFinFET respectively. This can be reasonably explained by the decay of saturation velocity in high temperature. The results obtained based on this methodology will help us on the understanding of the SHE impact on a nano-scaled FinFET device.
Analysis of an anomalous hump in gate current after dynamic negative bias stress in HfxZr1-xO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors
(1970-01-01)
Ho, Szu-Han
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Chang, Ting-Chang
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Wu, Chi-Wei
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Lo, Wen-Hung
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Chen, Ching-En
"This letter investigates a hump in gate current after dynamic negative bias stress (NBS) in HfxZr1-xO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. By measuring gate current under initial through body floating and source/drain floating, it shows that hole current flows from source/drain. The fitting of gate current-gate voltage characteristic curve demonstrates that Frenkel-Poole mechanism dominates the conduction. Next, by fitting the gate current after dynamic NBS, in the order of Frenkel-Poole then tunneling, the Frenkel-Poole mechanism can be confirmed. These phenomena can be attributed to hole trapping in high-k bulk and the electric field formula Ehigh-k epsilon(high-k) = Q + E-sio2 epsilon(sio2). (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4739525]"
Analysis of anomalous traps measured by charge pumping technique in HfO2/metal gate n-channel metal-oxide-semiconductor field-effect transistors
(2012-12-03)
Ho, Szu-Han
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Chang, Ting-Chang
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Lu, Ying-shin
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Lo, Wen-Hung
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Chen, Ching-En
This letter investigates anomalous traps measured by charge pumping technique in high voltage in HfO2/metal gate n-channel metal-oxide-semiconductor field-effect transistors. N-V-high level characteristic curves with different duty ratios indicate that the electron discharge time dominates the value of N for extra traps. By fitting ln (N (t(base level) = 2.5 mu s)-N (t(base level)))-Delta t(base level) at different temperatures and computing the equation t = tau(0) exp (alpha(e,SiO2)d(SiO2) + alpha(e,HfO2)d(HfO2,trap)), results show that these extra traps measured by the charge pumping technique at high voltage can be attributed to high-k bulk shallow traps. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4769444]
Analysis of Oxide Trap Characteristics by Random Telegraph Signals in nMOSFETs With HfO2-Based Gate Dielectrics
(2016-04)
Chen, Ching-En
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Chang, Ting-Chang
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You, Bo
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Tsai, Jyun-Yu
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Lo, Wen-Hung
This letter investigates the oxide trap properties in n-channel metal-oxide-semiconductor field-effect transistors with HfO2 and Hf(1-x)ZrxO(2)/metal gate-stacks by an analysis of random telegraph signals. According to the multiphonon emission theory, the extracted relaxation energies show gate voltage dependence in devices with HfO2-based stacks. This dependence results from the different strengths of vibrations of the nearest neighbor Hf atoms of the oxygen vacancy in the immediate vicinity of the oxide trap. Furthermore, this dependence also induces an abnormal gate voltage dependence in terms of the activation energy required for electron capture. These results are confirmed by comparisons between two HfO2-based devices (HfO2 and Hf(1-x)ZrxO(2)).
Anomalous Gate Current Hump after Dynamic Negative Bias Stress and Negative-Bias Temperature-Instability in p-MOSFETs with HfxZr1-xO2 and HfO2/Metal Gate Stacks
(2013)
Ho, Szu-Han
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Chang, Ting-Chang
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Wu, Chi-Wei
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Lo, Wen-Hung
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Chen, Ching-En
In this study, the authors investigated an anomalous gate current hump after dynamic negative bias stress (NBS) and negative-bias temperature-instability (NBTI) in HfxZr1-xO2 and HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. This result is attributed to hole trapping in high-k bulk. Measuring gate current under initial through body floating and source/drain floating conditions indicates that holes flow from source/drain to gate. The fitting of the gate current-gate voltage characteristic curve demonstrates that Frenkel-Poole mechanism dominates the conduction under initial. Next, fitting the gate current after dynamic NBS and NBTI indicates Frenkel-Poole then tunneling mechanisms, finally returning to the Frenkel-Poole mechanism. These phenomena can be attributed to hole trapping in high-k bulk and the formula Ehigh-k epsilon(high-k) = Q + E-sio2 epsilon(sio2). To further understand the gate current hump, both Zr-undoped and 8 similar to 10% Zr-doped in high-k bulk devices were used for comparisons. These results indicate that initial gate current is also a significant factor in generating the anomalous gate current hump, and all results obey the hump generation condition of J(Tunneling) << J(Frenkel-Poole). (C) 2013 The Electrochemical Society. All rights reserved.
Charge trapping induced drain-induced-barrier-lowering in HfO2/TiN p-channel metal-oxide-semiconductor-field-effect-transistors under hot carrier stress
(2012-04-09)
Lo, Wen-Hung
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Chang, Ting-Chang
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Tsai, Jyun-Yu
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Dai, Chih-Hao
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Chen, Ching-En
This letter studies the channel hot carrier stress (CHCS) behaviors on high dielectric constant insulator and metal gate HfO2/TiN p-channel metal-oxide-semiconductor field effect transistors. It can be found that the degradation is associated with electron trapping, resulting in G(m) decrease and positive Vth shift. However, Vth under saturation region shows an insignificant degradation during stress. To compare that, the CHC-induced electron trapping induced DIBL is proposed to demonstrate the different behavior of Vth between linear and saturation region. The devices with different channel length are used to evidence the trapping-induced DIBL behavior. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3697644]
Charge trapping induced frequency-dependence degradation in n-MOSFETs with high-k/metal gate stacks
(2011-12-30)
Dai, Chih-Hao
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Chang, Ting-Chang
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Chu, Ann-Kuo
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Kuo, Yuan-Jui
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Hung, Ya-Chi
This letter investigates the reliability issues of HfO(2)/Ti(1-x)N(x) metal-oxide-semiconductor field effect transistor in terms of static and dynamic stress. The results indicate threshold voltage (V(th)) instability under dynamic stress is more serious than that under static stress, owning to transient charge trapping within high-k dielectric. Capacitance-voltage techniques verified that electron trapping under dynamic stress was located in high-k dielectric near the source/drain (S/D) overlap region, rather than the overall dielectric. Furthermore, the V(th) shift clearly increases with an increase in dynamic stress operation frequency. This phenomenon can be attributed to the fact that electrons injecting to the S/D overlap region have insufficient time to de-trap from high-k dielectric. We further investigated the impact of different Ti(1-x)N(x) composition of metal-gate electrode on charge trapping characteristics, and observed that V(th) shift decreases significantly with an increase in the ratio of nitride. This is because the nitride atoms diffusing from the metal gate fill up oxygen vacancies and reduce the concentration of traps in high-k dielectric. Crown Copyright (C) 2011 Published by Elsevier B.V. All rights reserved.
Effectiveness of Si thin buffer layer for selective SiGe epitaxial growth in recessed source and drain for pMOS
(2008-02-15)
Chenga, P. L.
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Liao, C. I.
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Chien, C. C.
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Yang, C. L.
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Ting, S. F.
Locally strained Si technology using embedded SiGe has been used to improve pMOSFET device performance through hole mobility enhancement. Embedded SiGe is achieved by selectively growing epitaxial SiGe film in recessed Si pMOSFET source and drain areas. Prior to selective SiGe epi growth, a thin layer of Si seed was employed to help nucleate following low-temperature selective SiGe epitaxial film in recessed. source and drain areas. In combination with pre-epi wet clean and low-temperature chemical bake, use of Si seed resulted in improved SiGe film morphology and micro-loading effect, and further improved device performance. (c) 2007 Elsevier B.V. All rights reserved.
Effects of fabrication method on defects induced by nitrogen diffusion to the hafnium oxide layer in metal-oxide-semiconductor field effect transistors
(2016-12-01)
Lu, Ying-Hsin
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Chang, Ting-Chang
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Ho, Szu-Han
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Chen, Ching-En
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Tsai, Jyun-Yu
This study investigates how different metal gate fabrication methods induce variations in the defects which result from nitrogen diffusing into the hafnium oxide layer in metal-oxide-semiconductor field effect transistors (MOSFETs). By using the different fabrication methods of pre-TaN, post-TaN and post-TiN annealing, the work-function difference between the gate material and the semiconductor can be adjusted, leading to apparent differences in threshold voltage (V-th). In addition, the results of slow and fast I-V NBTI measurements show that the amount of the bulk trapping in the post-TiN device is the highest, followed by the post-TaN device and then the pre-TaN device. In addition, a nitrogen interstitial defect phenomenon, resulting in a temporary shift of threshold voltage (V-th) which is highest in the post-TiN the lowest in the pre-TaN device, is determined by double sweep fast I-V measurements. (C) 2016 Elsevier B.V. All rights reserved.
Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks
(2014-10-06)
Tsai, Jyun-Yu
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Chang, Ting-Chang
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Chen, Ching-En
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Ho, Szu-Han
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Liu, Kuan-Ju
This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO2 interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks. (C) 2014 AIP Publishing LLC.
Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era
(2019-01-01)
Hsieh, E. R.
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Wang, H. W.
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Liu, C. H.
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Chung, Steve S.
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Chen, T. P.
In this work, a novel concept of 2-bit-per-cell (2B/C) is introduced to realize high-density OTP PUF from a new scheme of dielectric breakdown. This PUF shows 10(5)x of large window, good immunity to high-temperature disturbance, and excellent retention under 150 degrees C baking, which are particularly for automotive applications. In terms of security. this PUF exhibits near ideal normal distribution of hamming distance and narrow distribution of hamming weight. The bit error rates are low, 0.78% at 25 degrees C and 1.95% at 150 degrees C, benchmarked on a 256-bit array. Finally, the security test of this PUF against the hackers' attack from the machine learning process has been proved to have high security. Overall, the proposed 2B/C OTP PUF demonstrated great potential for IoT security in 5G era.
Enhanced gate-induced floating-body effect in PD SOI MOSFET under external mechanical strain
(2010-11-25)
Dai, Chih-Hao
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Chang, Ting-Chang
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Chu, Ann-Kuo
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Kuo, Yuan-Jui
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Chen, Shih-Ching
The influence of tensile mechanical strain on gate-induced floating-body effect (GIFBE) in advanced partially depleted SOI n-MOSFETs was investigated. Both drain current and mobility enhance after applying strain due to the reduction of average transfer effective mass. However, it was found that the GIFBE becomes serious under the mechanical strain. To explain this phenomenon, we first clarify the mechanism of GIFBE using different operation conditions. The experiment results indicate that the GIFBE can be attributed to the anode hole injection (AHI) rather than the widely accepted mechanism of electron band (EVB) tunneling. Based on the AHI model, the enhanced GIFBE under the mechanical strain is mainly due to the narrowing of band gap induced by the strain in the poly-gate. (C) 2010 Elsevier B.V. All rights reserved.