Browsing by Author "Cheng, SC"

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A comparison of block-matching algorithms for VLSI implementation
(1996)
Cheng, SC
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Hang, HM
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A comparison of block-matching algorithms mapped to systolic-array implementation
(1997-10-01)
Cheng, SC
;
Hang, HM
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電子工程學系及電子研究所
;
電信研究中心
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an evaluation of several well-known block-matching motion estimation algorithms from a system-level very large scale integration (VLSI) design viewpoint, Because a straightforward block-matching algorithm (BMA) demands a very large amount of computing power, many fast algorithms have been developed, However, these fast algorithms are often designed to merely reduce arithmetic operations without considering their overall performance in VLSI implementation, In this paper, three criteria are used to compare various block-matching algorithms: 1) silicon area, 2) input/output requirement, and 3) image quality. A basic systolic array architecture is chosen to implement all the selected algorithms, The purpose of this study is to compare these representative BMA's using the aforementioned criteria. The advantages/disadvantages of these algorithms in terms of their hardware tradeoff are discussed. The methodology and results presented here provide useful guidelines to system designers in selecting a BMA for VLSI implementation.
Dual wavelength demultiplexing by coupling and decoupling of photonic crystal waveguides
(2004-03-22)
Chien, FSS
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Hsu, YJ
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Hsieh, WF
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Cheng, SC
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光電工程學系
We demonstrate that the fundamental mode of the two coupled photonic crystal waveguides (PCWs) can be odd parity in a triangular photonic crystal and their dispersion curves do intersect. Thus, the PCWs are decoupled at the crossing point. By employing the decoupling at the crossing-point frequency and ultra short coupling length for another frequency, we designed a dual-wavelength demultiplexer with a coupling length of only two wavelengths and output power ratio as high as 15 dB. A loop-shape PCW is adapted to eliminate the backward energy flow. (C) 2004 Optical Society of America.
Formation and properties of roughened poly-Si electrodes for high-density DRAMs
(1997)
Liu, HW
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Lin, ZJ
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Yu, SY
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Huang, SC
;
Cheng, SC
A novel structure, based upon phosphorus-implanted poly-Si films treated with phosphoric acid (H3PO4) and the standard RCA cleaning process, has been demonstrated as the bottom electrodes of DRAMs(1) stacked capacitors. After the H3PO4 treatment and the RCA cleaning process, micro-islands are formed on the poly-Si surface of the electrodes. For the capacitors with this novel structure, the capacitance value is 18.17 fF/mu m(2) and the effective oxide thickness is 18.9 Angstrom in comparison with conventional capacitors of 5.77 fF/mu m(2) and 59.5 Angstrom. The roughened poly-Si electrode can achieve a surface enlargement of 3.15 times. The leakage current density at +1.65V and -1.65V are 7.24 x 10(-8) A/cm(2) and -3.31 x 10(-8) A/cm(2), respectively, fulfilling the requirements of 256Mb DRAMs. Weibull plots of time-zero-dielectric-breakdown (TZDB) characteristics under ramping voltage test also show tight distribution and good electrical properties. It indicates that the phosphorus-implanted poly-Si films etched by H3PO4 and then cleaned with the standard RCA process can easily and simply increase the surface area and have good electrical properties fulfilling the requirements of 256Mb DRAMs and beyond.
High-efficiency coupling between external and photonic crystal waveguides by longitudinally shifting waveguide junctions
(2004-12-08)
Chang, CW
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Cheng, SC
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Hsieh, WF
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光電工程學系
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Department of Photonics
Longitudinally shifting waveguide junctions can achieve high efficiency light coupling from external silica waveguides into photonic crystal waveguides (PCWs) without requiring taper PCW structures in the waveguide junctions. Due to the periodic field distribution of PCWs along the propagation direction, maximum and minimum coupling efficiency occur when waveguide junctions are located near the peak and valley of the longitudinal mode profile, and coupling efficiency depends on both the localization of mode fields in PCWs and the group velocities of eigenmodes. Coupling efficiency of 86% between silicon/silica PCWs and external silica waveguides can be achieved without the need for special design in the junction region for the reduced-rod PCW. Due to large Bragg reflection, coupling of the band edge modes at the flat dispersion regions that possess small group velocities is inefficient. (C) 2004 Elsevier B.V. All rights reserved.
The impact of encoding algorithms on MPEG VLSI implementation
(1998)
Cheng, SC
;
Hang, HM
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The goal of this paper is to study the impact of MPEG encoding algorithms from a system-level design viewpoint. An area-time estimation tool is developed to extract the timing requirement and silicon area for various combinations of hardware modules and algorithms. After complemented the design of several modules in an MPEG encoder, we found that the motion estimation and rate control modules consume most part of the silicon area in the encoding chip. We also evaluated the entire chip area of a few cases for two picture formats. The methodology and results presented here should provide useful guidelines in selecting an appropriate MPEG encoding algorithm for VLSI design.
The impact of rate control algorithms on system-level VLSI design
(1998-12-01)
Cheng, SC
;
Hang, HM
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an evaluation of rate control algorithms from a system-level VLSI design viewpoint. Rate control in video coding has a significant influence on the coded bit rate and image quality. Many rate control algorithms have been proposed mainly focusing on the optimal rate-distortion performance without considering their performance on the VLS implementation. The purpose of this study is not to propose a hardware architecture for any specific algorithm but to study the algorithm impact on hardware design. Based on our finding, a system designer should choose an algorithm not only good in rate control performance but also good in hardware implementation. When implementing and comparing a few rate control algorithms using a generic processor structure, we found that, in addition to the ordinary computational complexity, the internal buffer size is also very critical in VLSI realization. Several picture sequences have been tested including one sequence constructed specifically to simulate a difficult case for rate control. In this paper, three different types of popular rate control algorithms have been analyzed based on their picture quality, the internal buffer size, and the hardware cost. The methodology and results presented here provide useful guidelines for selecting an appropriate rate control algorithm for system-level VLSI designers.
The impact of rate control algorithms on video codec hardware design
(1997)
Cheng, SC
;
Hang, HM
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交大名義發表
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電子工程學系及電子研究所
;
National Chiao Tung University
This paper presents an evaluation of rate control algorithms from a system-level VLSI design viewpoint. Rate control in video coding has a significant influence on the coded bits and image quality. Many rate control algorithms have been proposed mainly focusing on the optimal rate-distortion performance without considering their overall performance on the VLSI implementation. However, a system-level designer should design an algorithm not only good in performance but also good in implementation. In this paper, three different types of popular rate control algorithms have been analyzed based on their picture quality, the internal buffer size and the hardware cost. The methodology and results presented here should provide useful guidelines for selecting an appropriate rate control algorithm for system-level VLSI design.