Browsing by Author "Cheng, SM"

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A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damage
(1998-11-01)
Yih, CM
;
Cheng, SM
;
Chung, SS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new gate current model which considers the hot-electron induced oxide damage in n-MOSFET's was developed for the first time. The spatial distributions of oxide damage, including the interface state (N-it) and oxide trapped charge (Q(ox)), were characterized by using an improved gated-diode current measurement technique. A numerical model feasible for accurately simulating gate current degradation due to the stress generated N-it and Q(ox) has thus been proposed, Furthermore, the individual contributions of N-it and Q(ox) to the degradation of gate current can thus be calculated separately using these oxide damage. For devices stressed under maximum gate current biases, it was found that the interface state will degrade the gate current more seriously than that of the oxide trapped charge. In other words, the interface states will dominate the gate current degradation under I-G (max). Good agreement of the simulated gate current has been achieved by comparing with the measured data for pre-stressed and post-stressed devices. Finally, the proposed degradation model is not only useful for predicting the gate current after the hot-electron stress, but also provides a monitor that is superior to substrate current for submicron device reliability applications, in particular for EPROM and Flash EEPROM devices.
A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damage
(1998-11-01)
Yih, CM
;
Cheng, SM
;
Chung, SS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new gate current model which considers the hot-electron induced oxide damage in n-MOSFET's was developed for the first time. The spatial distributions of oxide damage, including the interface state (N-it) and oxide trapped charge (Q(ox)), were characterized by using an improved gated-diode current measurement technique. A numerical model feasible for accurately simulating gate current degradation due to the stress generated N-it and Q(ox) has thus been proposed, Furthermore, the individual contributions of N-it and Q(ox) to the degradation of gate current can thus be calculated separately using these oxide damage. For devices stressed under maximum gate current biases, it was found that the interface state will degrade the gate current more seriously than that of the oxide trapped charge. In other words, the interface states will dominate the gate current degradation under I-G (max). Good agreement of the simulated gate current has been achieved by comparing with the measured data for pre-stressed and post-stressed devices. Finally, the proposed degradation model is not only useful for predicting the gate current after the hot-electron stress, but also provides a monitor that is superior to substrate current for submicron device reliability applications, in particular for EPROM and Flash EEPROM devices.
A new bride damage characterization technique for evaluating hot carrier reliability of flash memory cell after P/E cycles
(1997)
Chung, SS
;
Yih, CM
;
Cheng, SM
;
Liang, MS
;
交大名義發表
A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cycles
(1999-09-01)
Chung, SS
;
Yih, CM
;
Cheng, SM
;
Liang, MS
;
電子工程學系及電子研究所
In this paper, we provide a methodology to evaluate the hot-carrier-induced reliability of hash memory cells after long-term program/erase cycles. First, the gated-diode measurement technique has been employed for determining the lateral distributions of interface state (N-it) and oxide trap charges (Q(ox)) under both channel-hot-electron (CHE) programming bias and source-side erase-bias stress conditions. A gate current model was then developed by including both the effects of N-it and Q(ox), Degradation of flash memory cell after P/E cycles due to the above oxide damage was studied by monitoring the gate current. For the cells during programming, the oxide damage near the drain will result in a programming time delay, and we found that the interface state generation iis the dominant mechanism. Furthermore, for the cells after long-term erase using source-side FN erase, the oxide trap charge will dominate the cell performance such as read-disturb. In order to reduce the read-disturb, source bias should be kept as low as possible since the larger the applied source erasing bias, the worse the device reliability becomes.
A novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12 similar to 16A) gate oxide
(2002)
Chung, SS
;
Chen, SJ
;
Yang, CK
;
Cheng, SM
;
Lin, SH
For the first time, an improved charge pumping (CP) method has been implemented for direct determination of the interface traps in ultra-short gate length CMOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12-16A gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has, been demonstrated successfully for various RTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. Moreover, it can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relating to the interface trap generation.
A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditions
(1997-11-01)
Cheng, SM
;
Yih, CM
;
Yeh, JC
;
Kuo, SN
;
Chung, SS
A new and accurate technique that allows the simultaneous determination of the spatial distributions of both interface states (N-it) and oxide charge (Q(ox)) will be presented. The gated-diode current measurement in combination with the gate-induced drain leakage (GIDL) current were performed to monitor the generation of both N-it and Q(ox) in n-MOSFET's. A special detrapping technique and simple calculations have been developed, from which the spatial distributions of both N-it and Q(ox) under various bias stress conditions, such as the hot-electron stress (I-G,I-max), I-B,I-max, and hot-hole stresses, can be determined. The calculation of gated-diode current by incorporating the extracted profiles of N-it and Q(ox) has been justified from numerical simulation. Results show very good agreement with the experimental results. The extracted interface damages for hot-electron and hot-hole stresses have very important applications for the study of hot-carrier reliability issues, in particular, on the design of flash EPROM, (EPROM)-P-2 cells since the above stress conditions, such as the I-G,I-max and hot-hole stress, are the major operating conditions for device programming and erasing, respectively.
A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditions
(1997-11-01)
Cheng, SM
;
Yih, CM
;
Yeh, JC
;
Kuo, SN
;
Chung, SS
A new and accurate technique that allows the simultaneous determination of the spatial distributions of both interface states (N-it) and oxide charge (Q(ox)) will be presented. The gated-diode current measurement in combination with the gate-induced drain leakage (GIDL) current were performed to monitor the generation of both N-it and Q(ox) in n-MOSFET's. A special detrapping technique and simple calculations have been developed, from which the spatial distributions of both N-it and Q(ox) under various bias stress conditions, such as the hot-electron stress (I-G,I-max), I-B,I-max, and hot-hole stresses, can be determined. The calculation of gated-diode current by incorporating the extracted profiles of N-it and Q(ox) has been justified from numerical simulation. Results show very good agreement with the experimental results. The extracted interface damages for hot-electron and hot-hole stresses have very important applications for the study of hot-carrier reliability issues, in particular, on the design of flash EPROM, (EPROM)-P-2 cells since the above stress conditions, such as the I-G,I-max and hot-hole stress, are the major operating conditions for device programming and erasing, respectively.
An intelligent GGSN dispatching mechanism for UMTS
(2005-05-16)
Cheng, SM
;
Lin, P
;
Tu, GH
;
Fu, LC
;
Liang, CF
3GPP proposed the Universal Mobile Telecommunication System (UMTS) to provide high-speed wireless transmission services to mobile users. To efficiently route the packets, the PDP contexts are maintained in the UE, SGSN, and GGSN in the UMTS network. Before beginning a session, the PDP Context Activation procedure is exercised to create the PDP contexts, where the SGSN selects one GGSN to serve the UE based on an IP list (for all GGSNs that can serve the UE). If the selected GGSN does not accept the request due to exception events, the SGSN chooses another GGSN until the list is exhausted, which may cause unbalance-loaded GGSNs, redundant traffic load to the network, introduce delay for the PDP context activation procedure, and thus decrease QoS for the UNITS network. To resolve the above issues, this paper proposes an intelligent GGSN dispatch mechanism 'IGD' with different sorting algorithms. The proposed mechanism is considered practical and easily installed in the existing UMTS network. We also conduct simulation experiments to investigate the performance of the IGD mechanism. (c) 2004 Elsevier B.V. All rights reserved.
Designing authentication protocols for third generation mobile communication systems
(2005-03-01)
Cheng, SM
;
Shieh, SP
;
Yang, WH
;
Lee, FY
;
Luo, JN
Security is considered an important issue for mobile communication systems. In particular, the design of authentication mechanisms has received considerable research interest recently. However, most of the current authentication schemes for mobile systems only have simple security functions and usually have some weaknesses, such as leakage of user identities and high update overhead of temporary identities. Moreover, these schemes cannot fulfill the security requirements specified in third generation mobile systems (IMT-2000, UMTS). In this paper, we propose a secure and flexible authentication framework for mobile communication systems. In the proposed framework, service providers can dynamically choose authentication mechanisms without the cooperation of network operators in visited domains. Based on the new framework, a secure authentication protocol is proposed. The proposed protocol can satisfy the security requirements of third generation mobile systems and is secure against network attacks, such as the replay attack and substitution attack. In short, our approach is secure and practical such that it can satisfy the security requirements of third generation mobile communication systems.
Direct observation of the lateral nonuniform channel doping profile in submicron MOSFET's from an anomalous charge pumping measurement results
(1995)
Chung, SS
;
Cheng, SM
;
Lee, GH
;
Guo, JC
;
電子工程學系及電子研究所