Browsing by Author "Cheng, T"

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Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
(1996-09-01)
Ker, MD
;
Wu, CY
;
Cheng, T
;
Chang, HH
;
電子工程學系及電子研究所
Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed, The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit, Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected.
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
(1996-09-01)
Ker, MD
;
Wu, CY
;
Cheng, T
;
Chang, HH
;
電子工程學系及電子研究所
Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed, The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit, Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected.
Efficient layout style of cmos output buffer to improve driving capability of low-voltage submicron cmos IC's
(1995)
Ker, MD
;
Wu, CY
;
Cheng, T
;
Chang, HH
;
Wu, MJN