Browsing by Author "Cheng, Wei-Min"

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A Low-latency GALS Interface Implementation
(2010)
Chang, Yuan-Teng
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Chen, Wei-Che
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Tsai, Hung-Yue
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Cheng, Wei-Min
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Chen, Chang-Jiu
With the VLSI technology improving rapidly, SoC has been becoming the most important VLSI application. However, clock distribution and low power have already become the two most important issues in SoC design. In addition, it's also a very important issue to integrate IPs that can perform operations correctly with different clocks. Asynchronous circuits may resolve these problems by removing the "clock" signal. But it's too hard to implement the whole circuits with asynchronous circuit. The GALS (Globally-Asynchronous Locally-Synchronous) design methodology can balance this problem via separating each synchronous design with asynchronous interface. Thus, each part of the circuit can perform operations with its own clock. The communication between different parts of the circuit can be achieved via asynchronous channels. The GALS provides a reliable communication between different modules. However, the latency of GALS interface may cause performance degradation seriously. Thus how to reduce the latency of GALS interface is significant. In this paper, we implemented a small and simple stretchable-clock based GALS wrapper with low-latency in Verilog HDL and synthesized the design with TSMC 0.13 mu m cell library. We also showed that the wrapper can operate correctly with modules which operate with great different clock frequencies. In addition, we also recommend adding FIFO storage element on the transmission path.
A Pipelined Asynchronous 8051 Soft-core Implemented with Balsa
(2008)
Chen, Chang-Jiu
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Cheng, Wei-Min
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Tsai, Ruei-Fu
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Tsai, Hung-Yue
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Wang, Tuan-Chieh
Microcontrollers are widely used in many handheld devices and embedded systems. Thus, low power, reliability, and robustness have been becoming the critical issues for these microcontrollers. Asynchronous circuits may be one of the best solutions to answer these problems. It is widely known that the 8051 processor is the most popular 8-bit microcontroller; however, because of its CISC nature, the pipeline is not very easy to implement, especially for asynchronous circuits. In this paper, we propose a novel pipelined asynchronous 8051 microcontroller. The design is implemented with Balsa language which is a CSP-based asynchronous HDL, and synthesized into Xilinx netlist by Balsa synthesis tool. The design is compared with synchronous ones with Xilinx FPGA.
A Quasi-Delay-Insensitive Microprocessor Core Implementation for Microcontrollers
(2009-03-01)
Chen, Chang-Jiu
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Cheng, Wei-Min
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Tsai, Hung-Yue
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Wu, Jen-Chieh
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資訊工程學系
Microcontrollers are widely used on simple systems; thus, how to keep them operating with high robustness and low power consumption are the two most important issues It is widely known that asynchronous circuit is the best solution to address these two issues at the same time. However, it's not very easy to realize asynchronous circuit and certainly very hard to model processors with asynchronous pipeline. That's why most processors are implemented with synchronous circuit. There are several ways to model asynchronous pipeline. The most famous of all is the micropipeline; in addition, most micropipeline based asynchronous systems are implemented with single-rail bundled-delay model. However, we implemented our 8-bit microprocessor core for asynchronous microcontrollers with an alternative - the Muller pipeline. We implemented our microprocessor core with dual-rail quasi-delay-insensitive model with Verilog gate-level design. The instruction set for the target microprocessor core is compatible with PIC 18. The correctness was verified with ModelSim software, and the gate-level design was synthesized into Altera Cyclone FPGA. In fact, the model we used in this paper can be applied to implement other simple microprocessor core without much difficulty.
Efficient Packets Management over Wireless Heterogeneous Networks
(2009-01-01)
Chen, Yu-Chang
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Lai, Tai-An
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Cheng, Wei-Min
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資訊工程學系
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Department of Computer Science
With the wireless technology becoming more and more mature, uncountable numbers of wireless networks are used worldwide. Hence, QoS ( Quality of Service) has become the most important topic that have to be seriously considered, such as the jitter, the packet loss ratio and the transmission rate. In this paper, we propose an EPM (Efficient Packets Management) mechanism to improve the transmission quality in the wireless heterogeneous networks. The heterogeneous architecture which we propose is based upon the "WiMAX" (Worldwide Interoperability for Microwave Access) and the Wi-Fi with QoS specification (802.11e). We also propose a heterogeneous gateway named the Arbitrative Classify Gateway (AC-Gateway) in the wireless heterogeneous environment, and cooperate with our derived EPM mechanism to classify the streaming data from the media center, or the voice data from another base station (BS) according to the privilege. The packets will be scheduled efficiently and transmit correctly. Based on the architecture we propose, the transmission quality will be raised. Finally, we will give some powerful simulation results to prove our architecture works.
Reducing the TLB Context Switching Miss Ratio With Banked and Prefetching Mechanism
(2008-11-01)
Chen, Chang-Jiu
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Cheng, Wei-Min
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資訊工程學系
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Department of Computer Science
Address translations from virtual addresses to physical addresses are widely considered as one of the most important issue for memory system performance. In order to improve the performance, the Translation Lookaside Buffer (TLB) is used. Lots of different methodologies are proposed to reduce TLB misses. Most designs just simply try to increase the total size of their TLBs to reduce the capacity misses or just simply use the fully associativity to reduce the conflict misses. Furthermore, some designs even try to incorporate the operating system (OS) and TLBs with very complex methods. Only some studies consider influence of performance on the context switching issue. Most traditional designs just simply added some types of address space identifier within the TLB tags. Nevertheless, the worse case of all is the x86 architecture which flushes all its TLB entries on context switching. This paper proposes a banked TLB structure with prefetching mechanism to reduce the miss rate in context switching for 32K page size. All simulations were done with modified SimpleScalar 3.0d tool suite and SPEC95 benchmarks. The results show that the proposed mechanism can provide acceptable performance improvement than the worse case x86 style design. The miss rate may even be only 1/10 or less. Thus, the proposed architecture may be suitable to be implemented inside processors to reduce the context switching misses. Furthermore, we'll try to implement it inside our new asynchronous processor.
Self-Timed Torus Network with 1-of-5 Encoding
(2009)
Chang, Yuan-Teng
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Huang, Man-Chen
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Cheng, Wei-Min
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Tsai, Hung-Yue
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Chen, Chang-Jiu
Nowadays, MPSoCs or multicore processors have been becoming the major trend of system or processor designs. Thus the design of interconnection networks becomes the most important issue of all. However, lots of different problems may arise in the network design and they should be carefully handled. It is widely known that most of these problems can be resolved easily by asynchronous circuits. But because of the difficulties of implementation, still only some real implementations of asynchronous networks. In this paper, we implemented a self-timed torus network with 1-of-5 DI encoding. The design was implemented in gate-level with Verilog HDL and synthesized with TSMC 0.13 mu m technology. The simulation shows that the network can operate correctly in 63.9 MHz.